CSDL - Proceedings V

Program Co-Chairs' Message (PDF)

pp. xviii

Conference Committee (PDF)

pp. xx

Steering Committee (PDF)

pp. xxiii

Technical Program Committee (PDF)

pp. xxiv

VLSI Design 1999 Fellowship Recipients (PDF)

pp. xxvii

VLSI Design 1999 Conference Awards (PDF)

pp. xxix

VLSI Design 1999 Design Contest Winners (PDF)

pp. xxx

Conference History (PDF)

pp. xxxi

Reviewers (PDF)

pp. xxxii

Tutorials

T1: Power Reduction Techniques for Portable DSP Applications (Abstract)

M. Mehendale

S.D. Sherlekar

pp. 3

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T2: (a) Theory and Applications of Cellular Automata for VLSI Design and Testing (Abstract)

K. Paul

pp. 4

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(b) Test Techniques and Trade-offs for Embedded Cores and Systems (Abstract)

R. Parekhji

pp. 5

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T3: (a) Computer-aided Design of RF Communication Systems: Techniques and Challenges (Abstract)

L. Nagel

J. Roychowdhury

pp. 6

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(b) Analog Circuits for Wireless Communications (Abstract)

R. Harjani

pp. 7

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T4: New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits (Abstract)

M. Breuer

S. Gupta

pp. 8

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T5: Core Based ASIC Design (Abstract)

F. Higgins

S. Bhawmik

pp. 10

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T6: (a) Partition, Packing and Clock Distribution-A New Paradigm of Physical Design (Abstract)

pp. 11

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(b) Low Power VLSI Signal Processing (Abstract)

K. Roy

K. Muhammad

pp. 12

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Intel India Development Center

KEYNOTE ADDRESS

Computing and Communication in the New Millennium (Abstract)

Avtar Saini

pp. 15

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Wireless Market Evolution

Thursday Plenary Talks: Chair: V. D. Agrawal, Bell Labs., Lucent Technologies

EDA-The Next Generation (Abstract)

Ajoy Bose

pp. 19

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IP Reuse in System on a Chip Design (Abstract)

pp. 20

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Session 1A: Low Power Design: Chairs: K. Roy, Purdue University: A. Chandrakasan, Massachusetts Institute of Technology

Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs (Abstract)

Liqiong Wei, Purdue University

Kaushik Roy, Purdue University

Vivek K. De, Intel Corp.

pp. 24

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Low Power Realization of Residue Number System Based FIR Filters (Abstract)

M.N. Mahesh, Texas Instruments, India Ltd.

Mahesh Mehendale, Texas Instruments, India Ltd.

pp. 30

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An Assertion Based Technique for Transistor Level Dynamic Power Estimation (Abstract)

S. Savithri, Motorola India Electronics Ltd.

R. Venkatesan, Motorola India Electronics Ltd.

S. Bhaskar, Motorola India Electronics Ltd.

pp. 34

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Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design (Abstract)

Russell Henning, Arizona State University

Chaitali Chakrabarti, Arizona State University

pp. 38

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A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25?m SOI Technology (Abstract)

pp. 44

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Energy Aware Software (Abstract)

Amit Sinha, Massachusetts Institute of Technology

Anantha P. Chandrakasan, Massachusetts Institute of Technology

pp. 50

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Session 1B: Formal Verification: Chairs: S. Malik, Princeton University: P. Dasgupta, Indian Institute of Technology

Performance and Functional Verification of Microprocessors (Abstract)

P. Bose, IBM T. J. Watson Research Center

J.A. Abraham, IBM T. J. Watson Research Center

pp. 58

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Automatic Component Matching Using Forced Simulation (Abstract)

Partha S Roop, University of New South Wales

A. Sowmya, University of New South Wales

S. Ramesh, Indian Institute of Technology

pp. 64

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Status Condition Analysis during Data Path Verification of Sequential Circuits (Abstract)

D Sarkar, Indian Institute of Technology

pp. 70

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Modeling VHDL in Multiclock ESTEREL (Abstract)

Basant Rajan, Tata Institute of Fundamental Research

R.K. Shyamasundar, Tata Institute of Fundamental Research

pp. 76

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Formal Verification of Synthesized Mixed Signal Designs Using *BMDs (Abstract)

Abhijit Ghosh, University of Cincinnati

Ranga Vemuri, University of Cincinnati

pp. 84

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Session 1C: Embedded Systems I: Chairs: R. Moona, Indian Institute of Technology P.P. Das, Alumnus Software

Interface Synthesis: Issues and Approaches (Abstract)

Arvind Rajawat, Indian Institute of Technology

M. Balakrishnan, Indian Institute of Technology

Anshul Kumar, Indian Institute of Technology

pp. 92

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Processor Evaluation in an Embedded Systems Design Environment (Abstract)

T. Vinod Kumar Gupta, Indian Institute of Technology

Purvesh Sharma, Indian Institute of Technology

M Balakrishnan, Indian Institute of Technology

Sharad Malik, Princeton University

pp. 98

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Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel (Abstract)

Rainer Schaffer, Dresden University of Technology

Renate Merker, Dresden University of Technology

Francky Catthoor, IMEC and Katholieke University Leuven

pp. 104

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Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming (Abstract)

Aviral Shrivastava, Indian Institute of Technology

Mohit Kumar, Indian Institute of Technology

Sanjiv Kapoor, Indian Institute of Technology

Shashi Kumar, Indian Institute of Technology

M. Balakrishnan, Indian Institute of Technology

pp. 110

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COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems (Abstract)

Robert P. Dick, Princeton University

Niraj K. Jha, Princeton University

pp. 114

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Session 2A: Digital Imaging I: Chairs: M.K. Kundu, Indian Statistical Institute S. Gupta, Intel

Challenges of Merging Digital Imaging and Wireless Communication (Abstract)

Werner Metz, Intel Corporation

Tinku Acharya, Intel Corporation

pp. 122

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Design of an ASIC for Straight Line Detection in an Image (Abstract)

A.K. Majumdar, Indian Institute of Technology

Nirav Patel, Lucent Technologies

pp. 128

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Digital Imaging with Wireless Data Services (Abstract)

Sandip Sarkar, QUALCOMM Inc.

pp. 134

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GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images (Abstract)

Kolin Paul, Bengal Engineering College (Deemed University)

Ranadeep Ghosal, Bengal Engineering College (Deemed University)

Biplab Sikdar, Bengal Engineering College (Deemed University)

Santashil Pal Chaudhuri, Indian Institute of Technology

D. Roy Choudhury, Indian Institute of Technology

pp. 140

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Scalable Pipelined Micro-Architecture for Wavelet Transform (Abstract)

Kolin Paul, Bengal Engineering College (Deemed University)

P. Pal Chaudhuri, Bengal Engineering College (Deemed University)

D. Roy Chowdhury, Indian Institute of Technology

pp. 144

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Interconnect Statistical Modeling: Structures and Measurement Methodologies (PDF)

Session 2B: Signal Integrity I: Chairs: S. Sapatnekar, University of Minnesota U. Narayanan, Intel

Akis Doganis, Mentor Graphics

pp. 150

Design and Analysis of Power Distribution Networks with Accurate RLC Models (Abstract)

Rajat Chaudhry, Motorola

Rajendran Panda, Motorola

Tim Edwards, Motorola

David Blaauw, Motorola

pp. 151

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A Methodology for the Placement and Optimization of Decoupling Capacitors for Gigahertz Systems (Abstract)

Jinseong Choi, Georgia Institute of Technology

Sunjun Chun, Georgia Institute of Technology

Nanju Na, Georgia Institute of Technology

Madhavan Swaminathan, Georgia Institute of Technology

Larry Smith, Georgia Institute of Technology

pp. 156

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Inductive Noise Reduction at the Architectural Level (Abstract)

Mondira Deb Pant, Georgia Institute of Technology

Pankaj Pant, Georgia Institute of Technology

D. Scott Wills, Georgia Institute of Technology

Vivek Tiwari, Intel Corporation

pp. 162

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Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits (Abstract)

Shiyou Zhao, Purdue University

Kaushik Roy, Purdue University

pp. 168

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Session 2C: Testing I: Chairs: S.M. Reddy, University of Iowa D.K. Das, Jadavpur University

Manufacturing and Test Considerations in System-On-Chip Designs (Abstract)

M. d'Abreu, Level One Communications Inc.

pp. 176

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Cost Trade-Offs in System On Chip Designs (Abstract)

J. Khare, Level One Communications

H. T. Heineken, Level One Communications

M. d'Abreu, Level One Communications

pp. 178

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Manufacturability and Testability Oriented Synthesis (Abstract)

S.A. Shaikh, Level One Communications, Inc.

J. Khare, Level One Communications, Inc.

H.T. Heineken, Level One Communications, Inc.

pp. 185

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Maximizing Wafer Productivity Through Layout Optimization (Abstract)

C. Ouyang, Level One Communications, Inc.

H.T. Heineken, Level One Communications, Inc.

J. Khare, Level One Communications, Inc.

S. Shaikh, Level One Communications, Inc.

M d'Abreu, Level One Communications, Inc.

pp. 192

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Hierarchical Test Generation for Systems On a Chip (Abstract)

Raghuram S. Tupuri, Advanced Micro Devices

Jacob A. Abraham, University of Texas at Austin

Daniel G. Saab, Case Western Reserve University

pp. 198

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Session 3A: High-level Synthesis: Chairs: N.K. Jha, Princeton University A. Kumar, Indian Institute of Technology

A Genetic Algorithm for the Synthesis of Structured Data Paths (Abstract)

C. Mandal, Brunel University

R.M. Zimmer, Brunel University

pp. 206

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A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures (Abstract)

Sriram Govindarajan, University of Cincinnati

Vinoo Srinivasan, University of Cincinnati

Preetham Lakshmikanthan, University of Cincinnati

Ranga Vemuri, University of Cincinnati

pp. 212

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High-Level Synthesis with Variable-Latency Components (Abstract)

Vijay Raghunathan, Indian Institute of Technology

Srivaths Ravi, Princeton University

Ganesh Lakshminarayana, NEC USA

pp. 220

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CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis (Abstract)

Vamsi K. Srikantam, Hewlett Packard Laboratories

N. Ranganathan, University of South Florida

Srikanth Srinivasan, University of South Florida

pp. 228

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Design Partitioning on Single-Chip Emulation Systems (Abstract)

A. Ejnioui, University of South Florida

N. Ranganathan, University of South Florida

pp. 234

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Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization (Abstract)

Rajeev Murgai, Fujitsu Laboratories of America, Inc.

pp. 240

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Session 3B: Layout & Floorplanning: Chairs: R. Suaya, Mentor Graphics C. Peterson, Intel

Routing on Switch Matrix Multi-FPGA Systems (Abstract)

Abdel Ejnioui, University of South Florida

N. Ranganathan, University of South Florida

pp. 248

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A Transistor Level Placement Tool for Custom Cell Generation (Abstract)

R.K. Dash, Indian Institute of Technology

T. Pramod, Indian Institute of Technology

V. Vasudevan, Indian Institute of Technology

M. Ramakrishna, Indian Institute of Technology

pp. 254

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On the Transistor Sizing Problem (Abstract)

Abhijit Das, Motorola India Electronics Limited

pp. 258

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Evaluation of Various Routing Architectures for Multi-FPGA Boards (Abstract)

Sushil Chandra Jain, Indian Institute of Technology

Shashi Kumar, Indian Institute of Technology

Anshul Kumar, Indian Institute of Technology

pp. 262

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A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks (Abstract)

Yu-Liang Wu, Chinese University of Hong Kong

Wangning Long, University of California at Los Angeles

Hongbing Fan, Shandong University

pp. 268

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Topological Routing Amidst Polygonal Obstacles (Abstract)

Swarup Bhunia, Delsoft India Pvt. Ltd.

Subhashis Majumder, Delsoft India Pvt. Ltd.

Ayan Sircar, Delsoft India Pvt. Ltd.

Susmita Sur-Kolay, Indian Statistical Institute

Bhargab B. Bhattacharya, Indian Statistical Institute

pp. 274

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A Tight Area Upper Bound for Slicing Floorplans (Abstract)

Helvio P. Peixoto, University of Texas at Austin

Margarida F. Jacome, University of Texas at Austin

Ander Royo, Technical University of Madrid

pp. 280

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Session 3C: Testing II: Chairs: M. d'Abreu, Intel B.B. Bhattacharya, Indian Statistical Institute

A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity (Abstract)

Hideo Fujiwara, Nara Institute of Science and Technology

pp. 288

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Test Transformation to Improve Compaction by Statistical Encoding (Abstract)

Hideyuki Ichihara, Osaka University

Kozo Kinoshita, Osaka University

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

pp. 294

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Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency (Abstract)

Hiroki Wada, Nara Institute of Science and Technology

Toshimitsu Masuzawa, Nara Institute of Science and Technology

Kewal K. Saluja, Nara Institute of Science and Technology

Hideo Fujiwara, Nara Institute of Science and Technology

pp. 300

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Choice of Tests for Logic Verification and Equivalence Checking (Abstract)

Vishwani D. Agrawal, Bell Labs, Lucent Technologies

pp. 306

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Automatic Validation Test Generation Using Extracted Control Models (Abstract)

Rob Sumners, University of Texas at Austin

Jayanta Bhadra, University of Texas at Austin

Jacob Abraham, University of Texas at Austin

pp. 312

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Banquet Address

DSP-The Real Time Technology for the New Millennium (Abstract)

John Scarisbrick

Texas Instruments

pp. 321

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Friday Plenary Talk: Chair: P.P. Chakrabarti, Indian Institute of Technology

Surviving the SOC Revolution: The Platform Approach to SOC Design (Abstract)

Grant Martin

Cadence Design Systems

pp. 325

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Session 4A: Digital Imaging II: Chairs: A.K. Majumdar, Indian Institute of Technology T. Acharya, Intel

A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation (Abstract)

Sabyasachi Dey, Indian Statistical Institute

Bhargab B. Bhattacharya, Indian Statistical Institute

Malay K. Kundu, Indian Statistical Institute

Tinku Acharya, Intel Corporation

pp. 330

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Optimization of the One-Dimensional Full Search Algorithm and Implementation Using an EPLD (Abstract)

Rajesh T.N. Rajaram, Indian Institute Technology

Vinita Vasudevan, Indian Institute Technology

pp. 336

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A Single-Chip Programmable Digital CMOS Imager with Enhanced Low-Light Detection Capability (Abstract)

Bedabrata Pain, California Institute of Technology

Guang Yang, California Institute of Technology

Monico Ortiz, California Institute of Technology

Kenneth McCarty, California Institute of Technology

Julie Heynssens, California Institute of Technology

Bruce Hancock, California Institute of Technology

Thomas Cunningham, California Institute of Technology

Chris Wrigley, California Institute of Technology

Charlie Ho, California Institute of Technology

pp. 342

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Session 4B: Design: Chairs: S. Srinivasan, Indian Institute of Technology M. Mehendale, Texas Instruments

Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications (Abstract)

Santanu Dutta, Philips Semiconductors

Deepak Singh, Philips Semiconductors

Essam Abu-Ghoush, Philips Semiconductors

Vijay Mehra, Philips Semiconductors

pp. 350

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Specification and Design of a Quasi-Delay-Insensitive Java Card Microprocessor (Abstract)

Fu-Chiung Cheng, Tatung University

Chuin-Ren Wang, Tatung University

pp. 356

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Trends in Communication Technology and its Impact on Semiconductor (Abstract)

Santanu Das, TranSwitch Corporation

pp. 362

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Session 4C: Signal Integrity II: Chairs: R. Roy, Intel S. Nag, Xilinx

Capturing the Effect of Crosstalk on Delay (Abstract)

Sachin S. Sapatnekar, University of Minnesota

pp. 364

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A Practical Approach to Crosstalk Noise Verification of Static CMOS Designs (Abstract)

N.S. Nagaraj, Texas Instruments Inc

Frank Cano, Texas Instruments Inc

Duane Young, Texas Instruments Inc

Deepak Vohra, Texas Instruments Inc

Manoj Das, Texas Instruments(India) Ltd.

pp. 370

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Inductance Characterization of Small Interconnects Using Test-Signal Method (Abstract)

Jeegar Tilak Shah, Indian Institute of Technology

Madhav P. Desai, Indian Institute of Technology

S. Sanyal, Tata Institute of Fundamental Research

pp. 376

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Session 5A: Testing III: Chairs: V.D. Agrawal, Bell Labs, Lucent Technologies I. Sengupta, Indian Institute of Technology

Zero-Aliasing Space Compression using a Single Periodic Output and its Application to Testing of Embedded Cores (Abstract)

Bhargab B. Bhattacharya, Indian Statistical Institute

Alexej Dmitriev, University of Potsdam

Michael Goessel, University of Potsdam

pp. 382

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Testing Interconnects in a System Chip (Abstract)

C.P. Ravikumar

Saurav Chopra

pp. 388

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On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits (Abstract)

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

pp. 392

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Resource-Constrained Compaction of Sequential Circuit Test Sets (Abstract)

Surendra K. Bommu, Synopsys Inc.

Srimat T. Chakradhar, NEC USA

Kiran B. Doreswamy, Intel Corp.

pp. 398

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Testing Flash Memories (Abstract)

Mohammad Gh. Mohammad, University of Wisconsin-Madison

Kewal K. Saluja, University of Wisconsin-Madison

Alex Yap, Motorola

pp. 406

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A Versatile BIST Technique Combining Test Registers and Accumulators (Abstract)

Frank Mayer, University of Karlsruhe

Albrecht P. Stroele, University of Karlsruhe

pp. 412

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Session 5B: Verification: Chairs: P. Bose, IBM A. Roy, Synopsys

Dataflow Analysis for Resource Contention and Register Leakage Properties (Abstract)

Subir K. Roy, Fujitsu Laboratories Limited

Hiroaki Iwashita, Fujitsu Laboratories Limited

Tsuneo Nakata, Fujitsu Laboratories Limited

pp. 418

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Retargetable Functional Simulator Using High Level Processor Models (Abstract)

Subhash Chandra, Indian Institute of Technology

Rajat Moona, Indian Institute of Technology

pp. 424

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State-Machine Based Logic Simulation Using Three Logic Values (Abstract)

Peter M. Maurer, University of Southern Florida

William J. Schilp, University of Southern Florida

pp. 430

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Hierarchical Error Diagnosis Targeting RTL Circuits (Abstract)

Vamsi Boppana, Fujitsu Laboratories of America, Inc.

Indradeep Ghosh, Fujitsu Laboratories of America, Inc.

Rajarshi Mukherjee, Fujitsu Laboratories of America, Inc.

Jawahar Jain, Fujitsu Laboratories of America, Inc.

Masahiro Fujita, Fujitsu Laboratories of America, Inc.

pp. 436

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Fast Error Diagnosis for Combinational Verification (Abstract)

A. Gupta, NEC USA

P. Ashar, NEC USA

pp. 442

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Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture (Abstract)

Y. Xia, NEC, USA

P. Ashar, NEC, USA

pp. 449

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Session 5C: Embedded Systems II: Chairs: D. Bhattacharya, Texas Instruments S.K. Nandy, Indian Institute of Science

Efficient Implementation of ADPCM Codec (Abstract)

Anil Sharma

C.P. Ravikumar

pp. 456

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Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems (Abstract)

pp. 462

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A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores (Abstract)

Karthikeyan Madathil, Texas Instruments (India) Ltd.

Jagdish C Rao, Texas Instruments (India) Ltd.

Subash Chander, Texas Instruments (India) Ltd.

Amitabh Menon, Texas Instruments (India) Ltd.

Avinash K Gautam, Texas Instruments (India) Ltd.

Amit M Brahme, Texas Instruments (India) Ltd.

H. Udayakumar, Texas Instruments (India) Ltd.

pp. 468

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Session 6A: Analog / Mixed-signal Circuits: Chair: S. Sen, University of Calcutta

SOI Digital Circuits: Design Issues (Abstract)

Ruchir Puri, IBM T. J. Watson Research Center

C.T. Chuang, IBM T. J. Watson Research Center

pp. 474

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Jitter Estimation Methodology for Clock Chips (Abstract)

Sanjeev Kumar Maheshwari, CYPRESS Semiconductors

R S Krishanan, CYPRESS Semiconductors

G.S. Visweswaran, Indian Institute of Technology, Delhi

pp. 480

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A 3.3V Compatible 2.5V TTL-to-CMOS Bidirectional I/O Buffer (Abstract)

Sanjeev Kumar Maheshwari, CYPRESS Semiconductors

G.S. Visweswaran, Indian Institute of Technology

pp. 484

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Silicon Heterostructure Devices for RF Wireless Communication (Abstract)

B. Senapati, Indian Institute of Technology

C.K. Maiti, Indian Institute of Technology

N.B. Chakrabarti, Indian Institute of Technology

pp. 488

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Design of OTA Based Field Programmable Analog Array (Abstract)

Baidyanath Ray, Bengal Engineering College (Deemed University)

P.Pal Choudhuri, Bengal Engineering College (Deemed University)

Prasanta Kumar Nandi, Bengal Engineering College (Deemed University)

pp. 492

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Convergence Issues in Resonant Tunneling Diode Circuit Simulation (Abstract)

Mayukh Bhattacharya, University of Michigan

Pinaki Mazumder, University of Michigan

pp. 499

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Session 6B: Synthesis and Timing Analysis: Chairs: N. Ranganathan, University of South Florida C.P. Ravikumar, Indian Institute of Technology

Spectral Theory of Disjunctive Decomposition for Balanced Boolean Functions (Abstract)

Bogdan J. Falkowski, Nanyang Technological University

Sudha Kannurao, Nanyang Technological University

pp. 506

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Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction (Abstract)

B. Suresh, Texas Instruments India

Biswadeep Chaterjee, Texas Instruments India

R. Harinath, Texas Instruments India

pp. 512

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Timing Analysis with Implicitly Specified False Paths (Abstract)

Eugene Goldberg, Cadence Berkeley Labs

Alexander Saldanha, Cadence Berkeley Labs

pp. 518

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Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors (Abstract)

Kamal S. Khouri, Princeton University

Niraj K. Jha, Princeton University

pp. 523

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Performance Analysis of Systems with Multi-Channel Communication Architectures (Abstract)

Kanishka Lahiri, University of California at San Diego

Sujit Dey, University of California at San Diego

Anand Raghunathan, NEC USA

pp. 530

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An ASIC for Cellular Automata Based Message Authentication (Abstract)

Prabir Dasgupta, Indian Institute of Technology

Santanu Chattopadhyay, Indian Institute of Technology

Indranil Sengupta, Indian Institute of Technology

pp. 538

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Session 6C: Testing IV: Chairs: H. Fugiwara, National Institute of Science and Technology P. Pal Chaudhuri, B.E. College

Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits (Abstract)

Prabir Dasgupta, Indian Institute of Technology

Santanu Chattopadhyay, Indian Institute of Technology

Indranil Sengupta, Indian Institute of Technology

pp. 544

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An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards (Abstract)

Sasikumar Cherubal, Georgia Institute of Technology

Abhijit Chatterjee, Georgia Institute of Technology

pp. 550

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Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator (Abstract)

Biplab K. Sikdar, Bengal Engineering College (D.U)

Kolin Paul, Bengal Engineering College (D.U)

Gosta Pada Biswas, Bengal Engineering College (D.U)

P. Pal Chaudhuri, Bengal Engineering College (D.U)

Vamsi Boppana, Fujitsu Laboratories of America Inc.

Cliff Yang, Fujitsu-WWSLT Ltd.

Sobhan Mukherjee, Fujitsu-WWSLT Ltd.

pp. 556

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Application of GF(2p) CA in Burst Error Correcting Codes (Abstract)

Kolin Paul, B. E. College (Deemed University)

Dipanwita Roy Chowdhury, Indian Institute of Technology

pp. 562

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Built-In Self-Test in Mixed-Signal ICs: A DTMF Macrocell (Abstract)

Gloria Huertas, Universidad de Sevilla

Diego Vazquez, Universidad de Sevilla

Adoración Rueda, Universidad de Sevilla

José L. Huertas, Universidad de Sevilla

pp. 568

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A Mixed-Signal BIST Scheme with Time-Division Multiplexing (TDM) Comparator and Counters (Abstract)

Jeongjin Roh, University of Texas at Austin

Jacob A. Abraham, University of Texas at Austin

pp. 572

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VLSI Design 1999 Paper (late arrival)

Design of Synchronous Action Systems (Abstract)

Juha Plosila, University of Turku

Tiberiu Seceleanu, Turku Center for Computer Science

pp. 578

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Author Index (PDF)

pp. 584

VLSI Design 2001 Call for Papers (PDF)

pp. 587