Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency

Hiroki Wada; Hideo Fujiwara; Toshimitsu Masuzawa; Kewal K. Saluja

doi:10.1109/ICVD.2000.812625

V
VLSID
2000
13th International Conference on VLSI Design
Abstract - Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency

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13th International Conference on VLSI Design

Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency

Calcutta, India

January 04-January 07

ISBN: 0-7695-0487-6

	ASCII Text	x
	Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara, "Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency," VLSI Design, International Conference on, pp. 300, 13th International Conference on VLSI Design, 2000.

	BibTex	x
	@article{ 10.1109/ICVD.2000.812625, author = {Hiroki Wada and Toshimitsu Masuzawa and Kewal K. Saluja and Hideo Fujiwara}, title = {Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2000}, issn = {1063-9667}, pages = {300}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812625}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency SN - 1063-9667 SP EP A1 - Hiroki Wada, A1 - Toshimitsu Masuzawa, A1 - Kewal K. Saluja, A1 - Hideo Fujiwara, PY - 2000 KW - Design for testability KW - Data path KW - Hierarchical test KW - Complete fault efficiency VL - 0 JA - VLSI Design, International Conference on ER -

Hiroki Wada, Nara Institute of Science and Technology

Toshimitsu Masuzawa, Nara Institute of Science and Technology

Kewal K. Saluja, Nara Institute of Science and Technology

Hideo Fujiwara, Nara Institute of Science and Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812625

In this paper, we propose a DFT method for RTL data paths to achieve 100% fault efficiency. The DFT method is based on hierarchical test and usage of a combinational ATPG tool. The DFT method requires lower hardware overhead and shorter test generation time than the full scan method, and also improves test application time drastically compared with the full scan method.

Index Terms:

Design for testability, Data path, Hierarchical test, Complete fault efficiency

Citation:

Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara, "Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency," vlsid, pp.300, 13th International Conference on VLSI Design, 2000

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