CSDL - Proceedings V

Program Co-Chairs' Message (PDF)

pp. xvi

Organizing Committee (PDF)

pp. xviii

Conference Steering Committee (PDF)

pp. xxi

Technical Program Committee (PDF)

pp. xxii

VLSI Design 1998 Fellowship Recipients (PDF)

pp. xxiv

1998 Conference Awards (PDF)

pp. xxvii

Design Contest and 1998 IEEE Fellow Awards (PDF)

pp. xxviii

Reviewers (PDF)

pp. xxix

Conference History (PDF)

pp. xxxi

Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis (Abstract)

Invited Talks

Invited Talk: The Information Appliance and Its Interface to the Analog World: Easy - Or Not So Easy

TCAD to ECAD I

pp. 6

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Incorporating Process Induced Effects into RC Extraction (Abstract)

K. Wong

pp. 12

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A New Methodology for Concurrent Technology Development and Cell Library Optimization (Abstract)

pp. 18

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Low Power I

A Low-Power Digital Camera-on-a-Chip Implemented in CMOS Active Pixel Approach (Abstract)

Bedabrata Pain, California Institute of Technology

Guang Yang, California Institute of Technology

Brita Olson, California Institute of Technology

Timothy Shaw, California Institute of Technology

Monico Ortiz, California Institute of Technology

Julie Heynssens, California Institute of Technology

Chris Wrigley, California Institute of Technology

Charlie Ho, California Institute of Technology

pp. 26

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A Low-Power Wireless Camera System (Abstract)

pp. 32

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Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation (Abstract)

Joao P. Marques Silva

pp. 37

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Low Power Code Generation of Multiplication-free Linear Transforms (Abstract)

M. Mehendale

S.D. Sherlekar

pp. 42

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Automatic Insertion of Gated Clocks at Register Transfer Level (Abstract)

N. Raghavan, Hewlett-Packard

V. Akella, Hewlett-Packard

S. Bakshi, Hewlett-Packard

pp. 48

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Compact, Ultra Low Power, Programmable Continuous-Time Filter Banks for Feedback Cancellation in Hearing Aid (Abstract)

K. Nair

R. Harjani

pp. 55

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A Low-Complexity, Reduced-Power Viterbi Algorithm (Abstract)

P.K. Singh

S. Jayasimha

pp. 61

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A Low Power 256 KB SRAM Design (Abstract)

pp. 67

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Testing I

Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits (Abstract)

pp. 72

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IDDQ-Testability of Tree Circuits (Abstract)

R.D. (Shawn) Blanton

pp. 78

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Test-Vector Prediction of M-Testable Iterative Arrays (Abstract)

M. Jamoussi

pp. 87

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Improving the Diagnosability of Digital Circuits (Abstract)

pp. 629

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A Comparative Study of Pseudo Stuck-At and Leakage Fault Model (Abstract)

S.T. Zachariah

S. Chakravarty

pp. 91

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Hierarchical Delay Fault Simulation (Abstract)

C.P. Ravikumar

Ajay Mittal

pp. 635

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A New Test Compression Scheme (Abstract)

pp. 95

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Invited Talk: Embedded Test for Systems-on-a-Chip

TCAD to ECAD II

Mini-Tutorial: IC Layout and Manufacturability: Critical Links and Design Flow Implications (Abstract)

A.B. Kahng

pp. 100

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New and Exact Filling Algorithms for Layout Density Control (Abstract)

pp. 106

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Silicon-Level Physical Verification of Sub Wavelength(tm) Designs (Abstract)

F.-C. Chang

M. Kwok

K. Rachlin

R. Pack

pp. 603

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Design for Manufacturing in the Semiconductor Industry: The Litho/Design Workshops (Abstract)

F.M. Schellenberg

pp. 111

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Interconnect Simple, Accurate and Statistical Models Using On-Chip Measurements for Calibration (Abstract)

A. Doganis

J.C. Chen

pp. 120

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Co-Design and Synthesis

MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign (Abstract)

pp. 128

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Processor Modeling for Hardware Software Codesign (Abstract)

V. Rajesh

R. Moona

pp. 132

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Synthesis of DMA Controllers from Architecture Independent Descriptions of HW/SW Communication Protocols (Abstract)

Mattias O'Nils

Axel Jantsch

pp. 138

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Hierarchical Conditional Dependency Graphs for Mutual Exclusiveness Identification (Abstract)

Apostolos A. Kountouris, Campus Universitaire de Beaulieu

Christophe Wolinski, Campus Universitaire de Beaulieu

pp. 146

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Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis. (Abstract)

Ludovic Jacomme, Universit? Pierre et Marie Curie

Frédéric Pétrot, Universit? Pierre et Marie Curie

Rajesh K. Bawa, Universit? Pierre et Marie Curie

pp. 151

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Invited Talk: Micro-2010: Lead Microprocessor for 2010 - Myth or Reality? (Abstract)

Manpreet S. Khaira

pp. 157

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Analog Design I

Exact Output Response Computation of RC Interconnects under Polynomial Input Waveforms (Abstract)

Satrajit Gupta

L.M. Patnaik

pp. 160

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Sub-Circuit Analysis for Power Supply Rejection Ratio in Regulated Cascode Operational Transconductance Amplifiers and Filters (Abstract)

A.B. Bhattacharyya

S. Dey

pp. 164

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Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks (Abstract)

S.H. Batterywala

H. Narayanan

pp. 169

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A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis (Abstract)

S . Savithri, Motorola India Electronics Ltd

D.G. Blaauw, Motorola India Electronics Ltd

A. Dharchoudhury, Advanced Systems Technology Lab

pp. 175

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Timed Circuit Synthesis Using Implicit Methods (Abstract)

pp. 181

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A New Approach for CMOS Op-Amp Synthesis (Abstract)

P. Mandal

V. Visvanathan

pp. 189

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Multi-Valued Logic

Multi-Valued Logic Synthesis (Abstract)

Robert K Brayton

Sunil P Khatri

pp. 196

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Alberto Sangiovanni-Vincentelli

Sequential Multi-Valued Network Simplification using Redundancy Removal (Abstract)

Sunil P Khatri

Robert K Brayton

pp. 206

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Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits (Abstract)

Shugang Wei

Kensuke Shimizu

pp. 212

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Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases (Abstract)

L. Macchiarulo

P. Civera

pp. 218

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Verification I

Controlling State Explosion in Static Simulation by Selective Composition (Abstract)

pp. 226

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FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model (Abstract)

pp. 232

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Efficient Simulation for Hierarchical and Partitioned Circuits (Abstract)

Peter M. Maurer

pp. 236

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Simulation and Modeling of a Multicast ATM Switch (Abstract)

A.C. Siddabathuni

M. Balakrishnan

pp. 242

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Invited Talk: Practical Use of Formal Verification - Where are we? Where do we go?

Testing II

VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits (Abstract)

Irith Pomeranz, University of Iowa

Sudhakar M. Reddy, University of Iowa

pp. 250

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Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations (Abstract)

pp. 256

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An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits (Abstract)

pp. 260

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A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems (Abstract)

Debaleena Das

Nur A. Touba

pp. 266

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Design and Test of MEMs (Abstract)

S. Mir

pp. 270

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Verification II

Formal Verification of an ARM Processor (Abstract)

V.A. Patankar

A. Jain

R.E. Bryant

pp. 282

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Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model Checking (Abstract)

Srivatsan Srinivasan, The University of Texas at Austin

Parminder Singh Chhabra, The University of Texas at Austin

Praveen Kumar Jaini, The University of Texas at Austin

Adnan Aziz, The University of Texas at Austin

Lizy John, The University of Texas at Austin

pp. 288

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An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays (Abstract)

pp. 294

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Superscalar Processor Validation at the Microarchitecture Level (Abstract)

Noppanunt Utamaphethai

R.D. (Shawn) Blanton

John P. Shen

pp. 300

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Verifying Tomasulo's Algoithm by Refinement (Abstract)

Tamarah Arons

Amir Pnueli

pp. 306

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Logic Verification of Very Large Circuits Using Shark (Abstract)

Jeremy Casas, Intel

Hannah Yang, Intel

Manpreet Khaira, Intel

Mandar Joshi, Intel

Thomas Tetzlaff, Intel

Steve Otto, Intel

Erik Seligman, Intel

pp. 310

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Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons (Abstract)

I. Sander

A. Jantsch

pp. 318

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Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams (Abstract)

pp. 324

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DSP

Array Index Allocation under Register Constraints in DSP Programs (Abstract)

A. Basu

R. Leupers

P. Marwedel

pp. 330

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Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs (Abstract)

D.V.R. Murthy, Indian Institute of Technology

S. Ramachandran, Indian Institute of Technology

S. Srinivasan, Indian Institute of Technology

pp. 336

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Design and Implementation of Viterbi Decoder Using FPGAs (Abstract)

B. Pandita

S.K. Roy

pp. 611

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Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms (Abstract)

pp. 340

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A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors (Abstract)

Avinash Gautam, Texas Instruments

Jagdish Rao, Texas Instruments

Rohit Rathi, Texas Instruments

Udayakumar H., Texas Instruments

pp. 346

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Synthesis of Configurable Architectures for DSP Algorithms (Abstract)

pp. 350

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Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures (Abstract)

pp. 358

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Logic Synthesis

Optimal Retiming for Initial State Computation (Abstract)

Peichen Pan, Intel Corporation

Guohua Chen, Clarkson University

pp. 366

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Performance Driven Synthesis for Pass-Transistor Logic (Abstract)

pp. 372

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A State Assignment Scheme Targeting Performance and Area (Abstract)

pp. 378

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Efficient Translation of Statecharts to Hardware Circuits (Abstract)

S. Ramesh, Indian Institute of Technology Bombay

pp. 384

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HEURISTIC TECHNOLOGY MAPPER FOR LUT BASED FPGAs (Abstract)

Chitrasena Bhat

Niranjan N. Chiplunkar

pp. 390

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Efficient Scheduling Techniques for ROBDD Construction (Abstract)

R. Murgai

J. Jain

M. Fujita

pp. 394

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The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches (Abstract)

P. Saxena

P. Pan

C.L. Liu

pp. 402

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Recent Advances in BDD Based Representations for Boolean Functions: A Survey (Abstract)

Amit Narayon

pp. 408

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Low Power II

POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing (Abstract)

X. Zhang

K. Roy

S. Bhawmik

pp. 416

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Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization (Abstract)

pp. 423

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Optimal Voltages and Sizing for Low Power (Abstract)

Mircea R. Stan, University of Virginia

pp. 428

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Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method (Abstract)

pp. 434

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Characterizing Individual Gate Power Sensitivity in Low Power Design (Abstract)

pp. 625

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Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages (Abstract)

pp. 440

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Physical Design I

GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs (Abstract)

Bulent Basaran, Intel Corporation

Kiran Ganesh, Intel Corporation

Raymond Lau, Intel Corporation

Artour Levin, Intel Corporation

Miles McCoo, Intel Corporation

Srinivasan Rangarajan, Intel Corporation

Naresh Sehgal, Intel Corporation

pp. 448

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Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells (Abstract)

Avaneendra Gupta, Cadence Design Systems

John P. Hayes, University of Michigan

pp. 453

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COST Circuit Optimization SysTem in ASIC Library Development Environment (Abstract)

pp. 460

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Interconnect Optimization Strategies for High-Performance VLSI Designs (Abstract)

pp. 464

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Modeling Crosstalk in Resistive VLSI Interconnections (Abstract)

S. Yang

pp. 470

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Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect (Abstract)

Noel Menezes, Intel Corporation

Chung-Ping Chen, Intel Corporation

pp. 476

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Testing III

A Test Generator for Segment Delay Faults (Abstract)

pp. 484

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A Complete Characterization of Path Delay Faults through Stuck-at Faults (Abstract)

Subhashis Majumder, Delsoft India Pvt. Ltd

Bhargab B. Bhattacharya, Indian Statistical Institute

Vishwani D. Agrawal, Bell Labs

Michael L. Bushnell, Rutgers University

pp. 492

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A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults (Abstract)

Jue Wu, Sun Microsystems

Elizabeth M. Rudnick, University of Illinois at Urbana

pp. 498

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Empirical Computation of Reject Ratio in VLSI Testing (Abstract)

Shashank K. Mehta, University of Nebraska-Lincoln

Sharad C. Seth, University of Nebraska-Lincoln

pp. 506

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Synthesis of Symmetric Functions for Path-Delay Fault Testability (Abstract)

Susanta Chakraborty, Kalyani University

Sandip Das, North Bengal University

Raja Rammohonpur

Debesh K. Das, Jadavpur University

Bhargab B. Bhattacharya, Indian Statistical Institute

pp. 512

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Pramodchandran N. Variyam

Test Generation for Analog Circuits Using Partial Numerical Simulation (Abstract)

Junwie Hou

Abhijit Chatterjee

pp. 518

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Digital Design and Applications

Design Considerations and Implementation of a High Performance Dynamic Register File (Abstract)

R. V. Joshi, IBM

W. Hwang, IBM

pp. 526

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A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata (Abstract)

K. Paul

pp. 532

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Lossy Compression of Images Using Logic Minimization (Abstract)

Jacob Augustine, Concordia University

William Lynch, Concordia University

Yuke Wang, Concordia University

Asim J. Al-Khalili, Concordia University

pp. 538

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Design, Simulation and Synthesis of an ASIC for Fractal Image Compression (Abstract)

pp. 544

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Invited Talk: Quantum Computation (Abstract)

Lov K. Grover

pp. 548

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Physical Design II

FAAR: A Router for Field-Programmable Analog Arrays (Abstract)

Sree Ganesan

Ranga Vemuri

pp. 556

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High Performance MCM Routing: A New Approach (Abstract)

Sandip Das, North Bengal University

Raja Rammohanpur

Subhas C. Nandy, Indian Statistical Institute

Bhargab B. Bhattacharya, Indian Statistical Institute

pp. 564

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Sequential Chaotic Annealing and its Application to Multilayer Channel Routing (Abstract)

Jayadeva

pp. 570

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Satisfiability-Based Detailed FPGA Routing (Abstract)

pp. 574

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TECHMIG: A Layout Tool for Technology Migration (Abstract)

P.K. Kar

S.K. Roy

pp. 615

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Improved Effective Capacitance Computations for Use in Logic and Layout Optimization (Abstract)

A.B. Kahng, Silicon Graphics, Inc.

S. Muddu, Silicon Graphics, Inc.

pp. 578

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Analog Design II

Analyzing Forced Oscillators with Multiple Time Scales (Abstract)

Onuttom Narayan, University of California at Santa Cruz

Jaijeet Roychowdhury, Bell Labs

pp. 621

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A Semi-Digital Delay Locked Loop for Clock Skew Minimization (Abstract)

Joonbae Park, Seoul National University

Yido Koo, Seoul National University

Wonchan Kim, Seoul National University

pp. 584

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Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis (Abstract)

pp. 589

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Test Generation for Analog Circuits Using Partial Numerical Simulation (Abstract)

P.N. Variyam

J. Hou

A. Chatterjee

pp. 597

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Tutorials:

CAD Techniques for Embedded System Design (PDF)

pp. 608

Manufacturability of Mixed Signal Systems (PDF)

pp. 608

Low Power Design Methodologies for Systems-on-Chips (PDF)

pp. 609

Verification of Systems-on-Chip Designs (PDF)

pp. 609

VLSI Signal Processing in FPGAs (PDF)

pp. 609

Built-In Self-Test for Systems on Silicon (PDF)

pp. 609-610

Author Index (PDF)

pp. 640