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- VLSID
- 1998
- Eleventh International Conference on VLSI Design: VLSI for Signal Processing
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Eleventh International Conference on VLSI Design: VLSI for Signal Processing India January 04-January 07 ISBN: 0-8186-8224-8 Table of Contents
 | Session 1: Plenary Session |
| Session 2: Low Power Design Methodologies: Chair: V. Tiwari, Intel Corporation, USA |
| Session 3: Physical Design: Chair: S. Raman, Motorola, USA |
| Session 4: System Design and Synthesis: Chair: P. Banerjee, Northwestern University, USA |
| Session 5: Digital Signal Processing: Chair: M. Desai, IIT, Mumbai, India |
| Session 6: Analog Techniques: Chair: V. Gopinathan, Lucent Technologies, USA |
| Session 7: Test Synthesis: Chair: S.M. Reddy, University of Iowa, USA |
| Session 8: Logic Level CAD: Chair: A. Saldanha, Cadence Berkeley Labs, USA |
| Session 9: Analog / Physical Design: Chair: K. Radhakrishna Rao, IIT, Madras, India |
| Session 10: Topics in Testing: Chair: M.L. Bushnell, Rutgers University, USA |
| Session 12: Banquet Session |
| Session 13: Plenary Session |
| Session 14: VLSI Architecture and Arithmetic: Chair: H. Selvaraj, Monash University, Australia |
A. Agarwal, Thapar Institute of Enginnering and Technology pp. 312
B. Laurent, Institut National Polytechnique de Grenoble / CSI
G. Bosco, Institut National Polytechnique de Grenoble / CSI
G. Saucier, Institut National Polytechnique de Grenoble / CSI pp. 322
J.C. Mo, Bell-Labs, Lucent Technologies pp. 326
| Session 15: Simulation and Synthesis: Chair: M. Srivastava, University of California, Los Angeles, USA |
| Session 16: Delay Test and Defect Analysis: Chair: B.B. Bhattacharya, ISI, India |
Ajai Jain, Indian Institute of Technology Kanpur pp. 370
| Session 17: Reconfigurable Processors and ASIC Design: Chair: G.S. Visweswaran, IIT, Delhi, India |
| Session 18: Architecture and System Design Tools: Chair: B. Courtois, TIMA, France |
| Session 19: Simulation and Test: Chair: P.G. Poonacha, Silicon Automation Systems, India |
| Session 20: Circuit Analysis and Design: Chair: N. Weste, Macquarie University, Australia |
| Session 21: Logic and Circuit Synthesis: Chair: C. Eswaran, IIT Madras, India |
| Session 22: Design Verification: Chair: J. Jain, Fujitsu Labs of America, USA |
| Session 23: Panel Session | Usage of this product signifies your acceptance of the Terms of Use.
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