Novel Memory Bus Driver/Receiver Architecture for Higher Throughput

Gregory E. Beers; Lizy K. John

doi:10.1109/ICVD.1998.646614

V
VLSID
1998
Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Abstract - Novel Memory Bus Driver/Receiver Architecture for Higher Throughput

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Eleventh International Conference on VLSI Design: VLSI for Signal Processing

Novel Memory Bus Driver/Receiver Architecture for Higher Throughput

India

January 04-January 07

ISBN: 0-8186-8224-8

	ASCII Text	x
	Gregory E. Beers, Lizy K. John, "Novel Memory Bus Driver/Receiver Architecture for Higher Throughput," VLSI Design, International Conference on, pp. 259, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998.

	BibTex	x
	@article{ 10.1109/ICVD.1998.646614, author = {Gregory E. Beers and Lizy K. John}, title = {Novel Memory Bus Driver/Receiver Architecture for Higher Throughput}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1998}, issn = {1063-9667}, pages = {259}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646614}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Novel Memory Bus Driver/Receiver Architecture for Higher Throughput SN - 1063-9667 SP EP A1 - Gregory E. Beers, A1 - Lizy K. John, PY - 1998 VL - 0 JA - VLSI Design, International Conference on ER -

Gregory E. Beers, The University of Texas at Austin

Lizy K. John, The University of Texas at Austin

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646614

A high speed memory bus interface which enables greater throughput for data reads and writes is described in this paper. Current mode CMOS logic synthesis methods are used to implement multi-valued logic (MVL) functions to create a high bandwidth bus.First, a fundamental bi-directional data bus for multiple logic levels is presented Then a bi-directional data bus with impedance matching terminators is presented. Finally a novel Adaptive Multi-Level Simultaneous bi-directional Transceiver (AMLST) bus structure for cache or main memory is proposed. The proposed bus can balance the memory channel bandwidth with the instruction execution rate of modern processors. Despite the problems encountered in implementing complete systems with MVL circuits, among which are circuit speed and design automation support, there is great potential in the future for this approach.

Citation:

Gregory E. Beers, Lizy K. John, "Novel Memory Bus Driver/Receiver Architecture for Higher Throughput," vlsid, pp.259, Eleventh International Conference on VLSI Design: VLSI for Signal Processing, 1998

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