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Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Hyderabad, India
January 04-January 07
ISBN: 0-8186-7755-4
Table of Contents
TUTORIALS
SESSION 1: MONDAY KEYNOTE ADDRESS
Session 2: PHYSICAL DESIGN: : Chair: S. Sur-Kolay, Jadavpur Univ.,Calcutta, India: Coordinator: S. Maturi, National Semiconductor, USA
P. Mazumdar, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 10
J. Shi, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
A. Randhar, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
D. Bhatia, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
pp. 21
S. Patkar, Indian Inst. of Technol., Mumbai, India
S.H. Batterywala, Indian Inst. of Technol., Mumbai, India
M. Chandramouli, Indian Inst. of Technol., Mumbai, India
H. Narayanan, Indian Inst. of Technol., Mumbai, India
pp. 32
R.V. Raj, Semiconductor Complex Limited
N. S. Murty, Semiconductor Complex Limited
P.S. Nagendra Rao, Indian Institute of Science
L.M. Patnaik, Indian Institute of Science
pp. 38
SESSION 3: SYNTHESIS: Chair: B.Courtois, TIMA, France: Coordinator: R. Pokala, Mentor Graphics, USA
Madhav Y. Chikodikar, Silicon Automation Systems
Shridhar Laddha, Silicon Automation Systems
Ashish Sirasao, Silicon Automation Systems
pp. 57
Dong-Hyun Heo, University of Southern California
Alice Parker, University of Southern California
C.P. Ravikumar, Indian Institute of Technology
pp. 62
M. Singh, Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
S.M. Nowick, Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
pp. 76
SESSION 4: Delay Test and Timing: Chair: K.K. Jain, Temic Usha, Gurgaon, India: Coordinator: M.V.V. Prasad, GITAM Engineering College, Andhra Univ., Visakhapatnam, India
S. Kajihara, Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Japan
K. Kinoshita, Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Japan
I. Pomeranz, Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Japan
S.M. Reddy, Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Japan
pp. 82
M.K. Srinivas, CAIP Center, Rutgers Univ., Piscataway, NJ, USA
M.L. Bushnell, CAIP Center, Rutgers Univ., Piscataway, NJ, USA
V.D. Agrawal, CAIP Center, Rutgers Univ., Piscataway, NJ, USA
pp. 88
Bernd Becker, Albert-Ludwigs-University
Rolf Drechsler, Albert-Ludwigs-University
Sudhakar M. Reddy, University of Iowa
pp. 101
Wen-Ben Jone, National Chung-Cheng University
Yun-Pan Ho, National Chung-Cheng University
Sunil R. Das, National Chung-Cheng University
pp. 106
A. Dharchoudhuri, Adv. Design Technol., Motorola Inc., Austin, TX, USA
S. M. Kang, Adv. Design Technol., Motorola Inc., Austin, TX, USA
pp. 111
SESSION 5: HIGH-LEVEL SYNTHESIS: Chair: A. Kumar, IIT New Delhi, India: Coordinator: K.V. Rao, KL College of Engineering, Nagarjuna Univ., Vijayawada, India
C.P. Ravikumar, Indian Institute of Technology
R. Aggarwal, University of Minnesota
C. Sharma, Indian Institute of Management
pp. 118
Mahesh Mehendale, Texas Instruments (India) Ltd.
S.D. Sherlekar, Indian Institute of Technology
G. Venkatesh, Indian Institute of Technology
pp. 124
Heman Khanna, Cadence Design Systems (I) Pvt. Ltd.
M. Balakrishnan, I.I. T. Delhi, New Delhi 110016
pp. 130
A.R. Naseer, Indian Institute of Technology
M. Balakrishnan, Indian Institute of Technology
Anshul Kumar, Indian Institute of Technology
pp. 134
M. Vootukuru, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
R. Vemuri, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
N. Kumar, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
pp. 140
SESSION 6: HW-SW CODESIGN: Chair: M. Mehendale, TI, India: Coordinator: K. Lal Kishore, JNT Univ., Hyderabad, India
S. Sarkar, Vetri Software Ltd., Madras, India
A. Basu, Vetri Software Ltd., Madras, India
A.K. Majumdar, Vetri Software Ltd., Madras, India
pp. 151
D. Saha, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
A. Basu, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
R.S. Mitra, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 155
J.M. Mendias, Dept. de Inf. y Autom., Univ. Complutense de Madrid, Spain
R. Hermida, Dept. de Inf. y Autom., Univ. Complutense de Madrid, Spain
M. Fernández, Dept. de Inf. y Autom., Univ. Complutense de Madrid, Spain
pp. 161
SESSION 7: LOW-POWER DESIGN:Chair: A.K. Majumdar, IIT Kharagpur, India: Coordinator: C.H.D.V. Pardesi Rao, JNT Univ.,Hyderabad, India
N. Sankarayya, Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy, Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
D. Bhattacharya, Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 174
P. Patil, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
T. Chou, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
R. Roy, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 179
Vivek Tiwari, Intel Corp., Santa Clara, CA, USA
Ryan Donnelly, Intel Corp., Santa Clara, CA, USA
Sharad Malik, Intel Corp., Santa Clara, CA, USA
Ricardo Gonzalez, Intel Corp., Santa Clara, CA, USA
pp. 185
SESSIONS 8: PARALLEL EXHIBITOR PRESENTATIONS
SESSION 9: VERIFICATION: Chair: S.P. Rajan, Fujitsu Lab of America, USA: Coordinator: A.K. Pujari, Central Univ., Hyderabad, India
S. P. Rajan, Fujitsu Labs. of America, Santa Clara, CA, USA
N. Shankar, Fujitsu Labs. of America, Santa Clara, CA, USA
M.K. Srivas, Fujitsu Labs. of America, Santa Clara, CA, USA
pp. 208
G. Swamy, Res. Labs., Mentor Graphics Corp., Boston, MA, USA
pp. 213
Jawahar Jain, Fujitsu Labs. of America, Santa Clara, CA, USA
Amit Narayan, Fujitsu Labs. of America, Santa Clara, CA, USA
M. Fujital, Fujitsu Labs. of America, Santa Clara, CA, USA
A. Sangiovanni-Vincentelli, Fujitsu Labs. of America, Santa Clara, CA, USA
pp. 218
I. Chakrabarti, Indian Institute of Technology
D. Sarkar, Indian Institute of Technology
A. K. Majumdar, Indian Institute of Technology
pp. 226
R. Murgai, Fujitsu Labs. of America Inc., Santa Clara, CA, USA
M. Fujita, Fujitsu Labs. of America Inc., Santa Clara, CA, USA
pp. 232
S. Harikumer, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India
S. Kumar, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India
pp. 239
SESSION 10: VLSI SYSTEMS: Chair: L.M. Patnaik, IISc, Bangalore, India: Coordinator: T. Kishan Rao, ECIL, Hyderabad, India
Media Processors (Abstract)
S. Nanda, Software & Silicon Syst. Ltd., India
pp. 244
S. Bhattacharjee, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
S. Das, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
D. Saha, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
D. Roychowdhury, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P. Pal Chaudhuri, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 247
G. Ascia, Universita' di Catania
V. Catania, Universita' di Catania
G. Ficili, Universita' di Catania
pp. 253
G.J. Jeong, Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea
K.H. Kwon, Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea
M.K. Lee, Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea
S.H. An, Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea
pp. 257
M.B. Kamble, Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
K. Ghose, Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
pp. 261
SESSION 11: TESTABILITY ENHANCEMENT:Chair: S.M. Menon, SDSMT, Rapid City, USA.: Coordinator: C. Gauthron, CMC Ltd., Hyderabad, India.
R.M. Chou, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
K.K. Saluja, Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 274
M.F. Abdulla, Indian Institute of Technology
C.P. Ravikumar, Indian Institute of Technology
Anshul Kumar, Indian Institute of Technology
pp. 297
SESSION 12: BANQUET KEYNOTE
SESSION 13: Tuesday Keynote Address
SESSION 14: ASYNCHRONOUS DESIGN: Chair: K. Emerson, Mentor Graphics, Singapore: Coordinator: R. Apte, Duet Technologies, SJ, USA
F.-C. Cheng, Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
S.H. Unger, Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
M. Theobald, Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
W.-C. Cho, Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
pp. 322
Kamran Eshraghian, Edith Cowan University
Juan A. Montiel-Nelson, Universidad de Las Palmas de Gran Canaria
Saeid Nooshabadi, Northern Territory University
pp. 336
K. Nanda, Dept. of Electr. Eng., Indian Inst. of Technol., Kanpur, India
S.K. Desai, Dept. of Electr. Eng., Indian Inst. of Technol., Kanpur, India
S.K. Roy, Dept. of Electr. Eng., Indian Inst. of Technol., Kanpur, India
pp. 342
Raj S Mitra, Cadence Design Systems Pvt Ltd
Bishnupriya Bhattacharya, Cadence Design Systems Pvt Ltd
Luciano Lavagno, Cadence Berkeley Labs
pp. 348
SESSION 15: DIAGNOSIS: Chair: A. Jain, IIT Kanpur, India: Coordinator: S. Ramakrishnan, CMC Ltd. Hyderabad, India
D. Bhatia, ECECS Dept., Cincinnati Univ., OH, USA
pp. 356
G.P. Biswas, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
I. Sengupta, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 364
Gaurav Aggarwal, Indian Institute of Technology
Nitin Thaper, Indian Institute of Technology
Kamal Aggarwal, Indian Institute of Technology
M. Balakrishnan, Indian Institute of Technology
Shashi Kumar, Indian Institute of Technology
pp. 370
V. Boppana, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
I. Hartanto, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W.K. Fuchs, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 376
S. Venkataraman, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
W.K. Fuchs, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 381
SESSION 16: TEST AND FAULT MODELING: Chair: K. Kinoshita, Osaka Univ., Japan: Coordinator: A. Moghe, CMC Ltd., Hyderabad, India
H. Yoon, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
J.L.A. Hughes, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 393
B. Vinnakota, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
R. Harjani, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
W.-Y. Choi, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 398
P.N. Variyam, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 408
H. Jin, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
R.K. Iyer, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
M.C. Hsueh, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
pp. 413
SESSION 17: MIXED-SIGNAL DESIGN: Chair: N. Jain, Duet Technologies, Noida, India: Coordinator: R.V.B Chari, Osmania Univ., Hyderabad, India
V.R. Babu, Texas Instruments(India) Ltd.
B. Mazhari, Indian Institute of Technology
M.M. Hasan, Indian Institute of Technology
pp. 425
K.R. Shankar, Texas Instrum. India Ltd., Bangalore, India
K. Radhakrishna Rao, Texas Instrum. India Ltd., Bangalore, India
S. Venkatraman, Texas Instrum. India Ltd., Bangalore, India
pp. 435
K.Ravi Shanker, Indian Institute of Technology
V. Vasudevan, Indian Institute of Technology
pp. 439
SESSION 18: ARCHITECTURE: Chair: A. Pal, IIT Kharagpur, India: Coordinator: S.R. Ramaswamy, RCI, Hyderabad, India
Ashley Rasquinha, Ctr. for Microelectronics Research, Department of Com. Sci.and Engineering, Tampa, FL
N. Ranganathan, Ctr. for Microelectronics Research, Department of Com. Sci.and Engineering, Tampa, FL
pp. 446
S. Nooshabadi, Northern Territory University
J. A. Montiel-Nelson, Universidad de Las Palmas de Gran Canaria
G. S. Visweswaran, Indian Institute of Technology, Delhi
D. Nagchoudhurhi, Indian Institute of Technology, Delhi
pp. 451
Palash Sarkar, Indian Statistical Institute
Bimal K. Roy, Indian Statistical Institute
Pabitra Pal Choudhury, Indian Statistical Institute
pp. 457
T.C. Pimenta, Escola Fed. de Engenharia de Itajuba, Brazil
L.L.G. Vermaas, Escola Fed. de Engenharia de Itajuba, Brazil
P.C. Crepaldi, Escola Fed. de Engenharia de Itajuba, Brazil
R.L. Moreno, Escola Fed. de Engenharia de Itajuba, Brazil
pp. 461
Rana Barua, Indian Statistical Institute & SPIC & Michigan State University
Samik Sengupta, Indian Statistical Institute & SPIC & Michigan State University
pp. 465
SESSION 19: ATPG and FAULT SIMULATION: Chair: Y. Zorian, Lucent Tech., Princeton, USA: Coordinator: L. Shastry, DRDO, Hyderabad, India
I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 470
D. Krishnaswamy, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA.
M.S. Hsiao, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA.
V. Saxena, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA.
E.M. Rudnick, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA.
J.H. Patel, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA.
P. Banerjee, Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA.
pp. 475
C.P. Ravikumar, Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India
V. Jain, Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India
A. Dod, Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India
pp. 482
S.T. Chakradhar, Comput. & Commun. Res. Labs., NEC USA, Princeton, NJ, USA
V. Gangaram, Comput. & Commun. Res. Labs., NEC USA, Princeton, NJ, USA
S. Rothweiler, Comput. & Commun. Res. Labs., NEC USA, Princeton, NJ, USA
pp. 488
E.M. Rudnick, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 495
SESSION 20: SYNTHESIS and CAD: Chair: R. Apte, Duet Technologies Inc., San Jose, USA: Coordinator: J. Hebbar, NRSA, Hyderabad, India
H. Mecha, Departimento Inf. y Autom., Universidad Complutense de Madrid, Spain
M. Fernandez, Departimento Inf. y Autom., Universidad Complutense de Madrid, Spain
pp. 504
T.C. Wilson, Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
G.W. Grewal, Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
pp. 506
H. Mehta, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 509
R. Drechsler, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
pp. 511
J. Jacob, Indian Inst. of Sci., Bangalore, India
P.S. Sivakumar, Indian Inst. of Sci., Bangalore, India
V.D. Agrawal, Indian Inst. of Sci., Bangalore, India
pp. 514
Session 21: DESIGN AND IMPLEMENTATION: Chair: V. Visvanathan, IISc, Bangalore, India: Coordinator: S. Hari Rao, JNT Univ., Hyderabad, India
R. Maheshwari, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
S.S.S.P. Rao, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
E.G. Poonach, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
pp. 523
S. Mukherjee, Texas Instrum. India Ltd., Bangalore, India
C. Srinivasan, Texas Instrum. India Ltd., Bangalore, India
V. Pawar, Texas Instrum. India Ltd., Bangalore, India
S. Mathur, Texas Instrum. India Ltd., Bangalore, India
K. Godbole, Texas Instrum. India Ltd., Bangalore, India
E. Soenen, Texas Instrum. India Ltd., Bangalore, India
pp. 525
S. Chattopadhyay, Dept. of Comput. Sci. & Tech., Bengal Eng. Coll., Howrah, India
P. Pal Chaudhuri, Dept. of Comput. Sci. & Tech., Bengal Eng. Coll., Howrah, India
pp. 527
G. P. Biswas, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
I. Sengupta, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 529
R.K. Pal, Dept. of Comput. Sci., Calcutta Univ., India
S.P. Pal, Dept. of Comput. Sci., Calcutta Univ., India
A. Pal, Dept. of Comput. Sci., Calcutta Univ., India
pp. 531
SESSION 22: TEST and DFT: Chair: M.L. Bushnell, Rutgers Univ., USA: Coordinator: S. Karthik, Natsem India, Bangalore, India
H. Nguyen, Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee, Georgia Inst. of Technol., Atlanta, GA, USA
R. Roy, Georgia Inst. of Technol., Atlanta, GA, USA
pp. 537
Raghuram S. Tupuri, University of Texas at Austin
Jacob A. Abraham, University of Texas at Austin
pp. 540
C.R. Graham, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
E.M. Rudnick, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 542
S.M. Menon, Dept. of Electr. & Comput. Eng., South Dakota Sch. of Mines & Technol., Rapid City, SD, USA
Y. Malaiya, Dept. of Electr. & Comput. Eng., South Dakota Sch. of Mines & Technol., Rapid City, SD, USA
A.P. Jayasumana, Dept. of Electr. & Comput. Eng., South Dakota Sch. of Mines & Technol., Rapid City, SD, USA
pp. 545
C. Rama Mohan, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
S. Mitra, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P. Pal Chaudhuri, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 547
SESSION 23: PANEL DISCUSSION: THE FUTURE OF THE INDIAN INFORMATION TECHNOLOGY NDUSTRY - A CEO's ROUNDTABLE
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