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Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A General Reconfiguration Technique for Fault Tolerant Processor Architectures
Hyderabad, India
January 04-January 07
ISBN: 0-8186-7755-4
Eshwar Belani, University of California at Berkeley
Ravi Mittal, Indian Institute of Technology, Madras
In this paper we present a new approach for fault tolerance in VLSI processor architectures. The reconfiguration technique is a general one in the sense that it can be applied to any arbitrary architecture with any number of spares each of which may be connected to an arbitrary number of processing elements. The technique is composed of two stages, local and global reconfiguration. In the local reconfiguration stage, faulty cells are maximally mapped onto adjacent spares. In the global stage, the shortest path from a faulty cell to a spare is found and the spare is ``propagated'' to the faulty site by the logical displacement of processing elements along that path.
Citation:
Eshwar Belani, Ravi Mittal, "A General Reconfiguration Technique for Fault Tolerant Processor Architectures," vlsid, pp.360, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997
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