Delay-Insensitive Carry-Lookahead Adders

F.-C. Cheng; W.-C. Cho; S.H. Unger; M. Theobald

doi:10.1109/ICVD.1997.568098

V
VLSID
1997
Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Abstract - Delay-Insensitive Carry-Lookahead Adders

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Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Delay-Insensitive Carry-Lookahead Adders

Hyderabad, India

January 04-January 07

ISBN: 0-8186-7755-4

	ASCII Text	x
	F.-C. Cheng, S.H. Unger, M. Theobald, W.-C. Cho, "Delay-Insensitive Carry-Lookahead Adders," VLSI Design, International Conference on, pp. 322, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997.

	BibTex	x
	@article{ 10.1109/ICVD.1997.568098, author = {F.-C. Cheng and S.H. Unger and M. Theobald and W.-C. Cho}, title = {Delay-Insensitive Carry-Lookahead Adders}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1997}, issn = {1063-9667}, pages = {322}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568098}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Delay-Insensitive Carry-Lookahead Adders SN - 1063-9667 SP EP A1 - F.-C. Cheng, A1 - S.H. Unger, A1 - M. Theobald, A1 - W.-C. Cho, PY - 1997 KW - delays KW - delay-insensitive carry-lookahead adders KW - integer addition KW - digital computer systems KW - adder speed KW - logic complexity KW - average computation time KW - economic implementation KW - CMOS technology KW - time complexity VL - 0 JA - VLSI Design, International Conference on ER -

F.-C. Cheng, Dept. of Comput. Sci., Columbia Univ., New York, NY, USA

S.H. Unger, Dept. of Comput. Sci., Columbia Univ., New York, NY, USA

M. Theobald, Dept. of Comput. Sci., Columbia Univ., New York, NY, USA

W.-C. Cho, Dept. of Comput. Sci., Columbia Univ., New York, NY, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568098

Integer addition is one of the mast important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a delay insensitive, carry-lookahead adder in which the logic complexity is a linear function of n, the number of inputs, and the average computation time is proportional to the logarithm of the logarithm of n. We also show an economic implementation of this adder in CMOS technology.

Index Terms:

delays, delay-insensitive carry-lookahead adders, integer addition, digital computer systems, adder speed, logic complexity, average computation time, economic implementation, CMOS technology, time complexity

Citation:

F.-C. Cheng, S.H. Unger, M. Theobald, W.-C. Cho, "Delay-Insensitive Carry-Lookahead Adders," vlsid, pp.322, Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, 1997

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