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9th International Conference on VLSI Design: VLSI in Mobile Communication
Bangalore, INDIA
January 03-January 06
ISBN: 0-8186-7228-5
Table of Contents
Tutorial Pages
1995 Keynote Address
1996 Keynote Address
Session 1: Plenary Session: Invited Address
Session 2: VLSI for Mobile Communication I: Chair: Pradeep Shah, Texas Instruments, Inc., Dallas, Texas, USA
A. Sriram, Dept. of Electrical and Computer Engineering University of California at Irvine
Fadi J. Kurdahi, Dept. of Electrical and Computer Engineering University of California at Irvine
pp. 19
Bengt Svantesson, Electronic Systems Design Department of Electronics Royal Institute of Technology
Ahmed hemani, Electronic Systems Design Department of Electronics Royal Institute of Technology
Peter Ellerve, Electronic Systems Design Department of Electronics Royal Institute of Technology
Adam Postula, Electronic Systems Design Department of Electronics Royal Institute of Technology
Johnny OEberg, Electronic Systems Design Department of Electronics Royal Institute of Technology
Axel Jantsch, Electronic Systems Design Department of Electronics Royal Institute of Technology
Hannu Tenhunen, Electronic Systems Design Department of Electronics Royal Institute of Technology
pp. 23
C. Nagendra, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 29
Session 3: Placement and Routing:Chair: Jun-Dong Cho, Sung Kyun Kwan University, Korea
J.A. Chandy, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
P. Banerjee, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 37
S. Das, Dept. of Comput. Sci., North Bengal Univ., Darjeeling, India
B. Bhattacharya, Dept. of Comput. Sci., North Bengal Univ., Darjeeling, India
pp. 43
S.Q. Zheng, Dept. of Comput. Sci., Louisiana State Univ., Baton Rouge, LA, USA
J.S. Lim, Dept. of Comput. Sci., Louisiana State Univ., Baton Rouge, LA, USA
S.S. Iyengar, Dept. of Comput. Sci., Louisiana State Univ., Baton Rouge, LA, USA
pp. 49
Session 4: Built-In Self-Test and Diagnosis: Chair: Asoke K. Laha, Cadence Design Systems, Noida, India
T.J. Chakraborty, AT&T Bell Labs., Princeton, NJ, USA
V.D. Agrawal, AT&T Bell Labs., Princeton, NJ, USA
pp. 53
S. Nandi, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Guwahati, India
S. Chattopadhyay, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Guwahati, India
P.P. Chandhuri, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Guwahati, India
pp. 61
Session 5: Hardware/Software Co-Design: Chair: Anupam Basu, IIT, Kharagpur, India
D.V. Poornaiah, Transmission R&D, Indian Telephone Ind. Ltd., Bangalore, India
P.V.A. Mohan, Transmission R&D, Indian Telephone Ind. Ltd., Bangalore, India
pp. 69
J. Shu, University of Guelph, Ontario, Canada N1G-2W1 dbanerji@snowhite.cis.uoguelph.ca
T.C. Wilson, University of Guelph, Ontario, Canada N1G-2W1 dbanerji@snowhite.cis.uoguelph.ca
D.K. Banerji, University of Guelph, Ontario, Canada N1G-2W1 dbanerji@snowhite.cis.uoguelph.ca
pp. 73
Session 6: Analog Circuits: Chair: A.N. Chandorkar, IIT, Bomba, India
A.B. Bhattacharyya, Indian Inst. of Technol., New Delhi, India
R.S. Rana, Indian Inst. of Technol., New Delhi, India
S.K. Guha, Indian Inst. of Technol., New Delhi, India
R. Bahl, Indian Inst. of Technol., New Delhi, India
R. Anand, Indian Inst. of Technol., New Delhi, India
M.J. Zarabi, Indian Inst. of Technol., New Delhi, India
P.A. Govindacharyulu, Indian Inst. of Technol., New Delhi, India
U. Gupta, Indian Inst. of Technol., New Delhi, India
V. Mohan, Indian Inst. of Technol., New Delhi, India
J. Roy, Indian Inst. of Technol., New Delhi, India
A. Atri, Indian Inst. of Technol., New Delhi, India
pp. 85
J. Weiss, SGS-THOMSON Microelectronics F-38019 Grenoble Cedex - France.
B. Majoux, SGS-THOMSON Microelectronics F-38019 Grenoble Cedex - France.
G. Bouvier, LTIRF - INPG F-38031 Grenoble Cedex - France
pp. 99
Session 7: Automatic Test Pattern Generation: Chair: James Jacob, IISc, Bangalore, India
Session 8: High-Level Synthesis I: Chair: Shashi Kumar, IIT, New Delhi, India
Srinivas Katkoori, Laboratory for Digital Design Environments, ECE&CS Dept. University of Cincinnati skatkoor@ece.uc.edu ranga@ece.uc.edu
Jay Roy, Laboratory for Digital Design Environments, ECE&CS Dept. University of Cincinnati skatkoor@ece.uc.edu ranga@ece.uc.edu
Ranga Vemuri, Laboratory for Digital Design Environments, ECE&CS Dept. University of Cincinnati skatkoor@ece.uc.edu ranga@ece.uc.edu
Jay Roy, Triquest Design Automation Inc. San Jose, CA 95126 jroy@ix.netcom.com
pp. 126
Session 9: High-Performance Circuits: Chair: Rajeev Jain, University of California, Los Angeles, USA
Session 10: Sequential Automatic Test Pattern Generation: Chair: M.M. Hasan, IIT, Kanpur, India
D. R. Chakrabarti, Indian Institute of Technology ajain@iitk.ernet.in
Ajai Jain, Indian Institute of Technology ajain@iitk.ernet.in
pp. 174
Session 12: High-Level Synthesis II: Chair: Bhargab Bhattacharya, Indian Statistical Institute, Calcutta, India
Krzysztof Bilinski, Department of Electrical & Electronic Engineering University of Bristol Bristol BS8 1TR, United Kingdom
Erik L. Dagless, Department of Electrical & Electronic Engineering University of Bristol Bristol BS8 1TR, United Kingdom
Jonathan M. Saul, Oxford University Computing Laboratory
pp. 186
Naren Narasimhan, Department of ECECS University of Cincinnati naren@ece.uc.edu
Ranga Vemuri, Department of ECECS University of Cincinnati naren@ece.uc.edu
Jay Roy, Triquest Design Automation, San Jose, CA
pp. 198
Session 13: Field-Programmable Gate Arrays: Chair: Mahesh Mehendale, Texas Instruments, Bangalore, India
Takayuki Suyama, 2-2 Hikaridai Seika-cho Soraku-gun, Kyoto, JAPAN NTT Communication Science Laboratories
Hiroshi Sawada, 2-2 Hikaridai Seika-cho Soraku-gun, Kyoto, JAPAN NTT Communication Science Laboratories
Akira Nagoya, 2-2 Hikaridai Seika-cho Soraku-gun, Kyoto, JAPAN NTT Communication Science Laboratories
pp. 215
L.K. John, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 219
Fran Hanchek, University of Minnesota Department of Electrical Engineering e-mail: {hanchek, dutt}@ee.umn.edu
Shantanu Dutt, University of Minnesota Department of Electrical Engineering e-mail: {hanchek, dutt}@ee.umn.edu
pp. 225
Session 14: Mixed-Signal Design and Test: Chair: Radhakrishna Rao, IIT, Madras, India
A. Chatterjee, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
B. Kim, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
N. Nagi, Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 230
P. Mandal, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
V. Visvanathan, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
pp. 234
A.K. A. A'ain, Microelectronics Research Group, Engineering Department, Lancaster University, Lancaster, LA1 4YR, U. K
A. H. Bratt, Microelectronics Research Group, Engineering Department, Lancaster University, Lancaster, LA1 4YR, U. K
A. P. Dorey, Microelectronics Research Group, Engineering Department, Lancaster University, Lancaster, LA1 4YR, U. K
pp. 238
R. Ramadoss, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
M.L. Bushnell, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 242
Session 15: Logic Design and Synthesis: Chair: Sujit Dey, NEC, Princeton, New Jersey, USA
A. Narayan, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
S.P. Khatri, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
J. Jain, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
M. Fujita, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
R.K. Brayton, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
A. Sangiovanni-Vincentelli, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 249
Irith Pomeranz, Electrical and Computer Engineering Department University of Iowa
Sudhakar M. Reddy, Electrical and Computer Engineering Department University of Iowa
pp. 254
D.K. Das, Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India
B.B. Bhattacharya, Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India
pp. 260
N.N. Biswas, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
C. Srikanth, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
J. Jacob, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
pp. 264
Session 16: Architecture: Chair: K. Neelakantan, Advanced Num. Res. & Anal, Group, Hyderabad, India
S. Bhattacharjee, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
J. Bhattacharya, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
U. Raghavendra, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
D. Saha, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P. Pal Chaudhuri, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 270
M. P. Sebastian, Indian Institute of Science, Bangalore mpsebas, nagendra, lawrn @ee.iisc.ernet.in
P. S. Nagendra Rao, Indian Institute of Science, Bangalore mpsebas, nagendra, lawrn @ee.iisc.ernet.in
Lawrence Jenkins, Indian Institute of Science, Bangalore mpsebas, nagendra, lawrn @ee.iisc.ernet.in
pp. 276
V. Krishna, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, US
A. Ejnioui, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, US
N. Ranganathan, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, US
pp. 280
S. Ramanathan, Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
V. Visvanathan, Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
pp. 286
Session 17: Logic and Fault Simulation: Chair: Debashis Bhattacharya, Texas Instruments, Dallas, Texas, USA
L. Pappu, CAIP Center, Rutgers Univ., Piscataway, NJ, USA
M.L. Bushnell, CAIP Center, Rutgers Univ., Piscataway, NJ, USA
V.D. Agrawal, CAIP Center, Rutgers Univ., Piscataway, NJ, USA
M.K. Srinivas, CAIP Center, Rutgers Univ., Piscataway, NJ, USA
pp. 290
Peter M. Maurer, Dept. of Computer Science & Eng, University of South Florida, Tampa, FL
pp. 303
S. Sundaram, Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
L.M. Patnaik, Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
pp. 307
Session 18: VLSI in Communications and Applications: Chair: P.V. Ananda Mohan, Indian Telephone Ind, Bangalore, India
S. Samel, Katholieke Universiteit Leuven, Belgium
B. Gyselinckx, Katholieke Universiteit Leuven, Belgium
I. Bolsens, Katholieke Universiteit Leuven, Belgium
H. de Man, Katholieke Universiteit Leuven, Belgium
pp. 311
S. Kulkarni, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
F. Mazumder, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
G.I. Haddad, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 313
S. Chattopadhyay, Dept. of Comput. Sci. & Tech., Bengal Eng. Coll., Howrah, India
S. Mitra, Dept. of Comput. Sci. & Tech., Bengal Eng. Coll., Howrah, India
P. Pal Chaudhuri, Dept. of Comput. Sci. & Tech., Bengal Eng. Coll., Howrah, India
pp. 320
J. Pal Singh, Cadence Design Syst. Pvt. Ltd., Noida, India
A. Kumar, Cadence Design Syst. Pvt. Ltd., Noida, India
S. Kumar, Cadence Design Syst. Pvt. Ltd., Noida, India
pp. 322
Session 19: Low-Power and Analog Design: Chair: Anantha Chandrakasan, MIT, Cambridge, Massachusetts, USA
Vivek Tiwari, Princeton Univeristy vivek@ee.princeton.edu
Sharad Malik, Princeton Univeristy vivek@ee.princeton.edu
Andrew Wolfe, Princeton Univeristy vivek@ee.princeton.edu
Mike Tien-Chien Lee, Fujitsu Laboratories of America
pp. 326
Suresh Rajgopal, Microprocessor Technology Intel Corporation, Santa Clara
pp. 329
Sudhir Aggarwal, SGS-THOMSON Microelectronics Sector 16A, NOIDA-201301, INDIA
pp. 331
S.K. Gupta, Dept. of Electr. Eng., Indian Inst. of Technol., Kanpur, India
M.M. Hasan, Dept. of Electr. Eng., Indian Inst. of Technol., Kanpur, India
pp. 333
Session 20: Test and Logic Synthesis: Chair: Robert Grafton, National Science Foundation, Arlington, Virginia, USA
G. Enrique Fernandez, Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
R. Sridhar, Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
pp. 335
S.R. Das, Dept. of Electr. Eng., Ottawa Univ., Ont., Canada
N. Goel, Dept. of Electr. Eng., Ottawa Univ., Ont., Canada
W.B. Jone, Dept. of Electr. Eng., Ottawa Univ., Ont., Canada
A.R. Nayak, Dept. of Electr. Eng., Ottawa Univ., Ont., Canada
pp. 337
A. Jaekel, VLSI Research Group, University of Windsor, Windsor, Ontario,
G.A. Jullien, VLSI Research Group, University of Windsor, Windsor, Ontario,
S. Bandyopadhyay, VLSI Research Group, University of Windsor, Windsor, Ontario,
pp. 339
V.D. Agrawal, AT&T Bell Labs., Murray Hill, NJ, USA
D. Lee, AT&T Bell Labs., Murray Hill, NJ, USA
pp. 341
N. Vijaykrishnan, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
N. Ranganathan, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
pp. 343
Session 21: Low-Power Design: Chair: N.S. Murty, Semiconductor Complex Ltd., Bangalore, India
Jatan C. Shah, Department of Electrical and Computer Engineering Iowa State University
Sachin S. Sapatnekar, Department of Electrical and Computer Engineering Iowa State University
pp. 346
N. Chaddha, Comput. Syst. Lab., Stanford Univ., CA, USA
M. Vishwanath, Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 358
Chuan-Yu Wang, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
K. Roy, Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 364
M. Mehendale, Texas Instrum. (India) Ltd., Bangalore, India
S.D. Sherlekar, Texas Instrum. (India) Ltd., Bangalore, India
G. Venkatesh, Texas Instrum. (India) Ltd., Bangalore, India
pp. 370
Session 22: Asynchronous Circuits, Retiming, and Paritioning: Chair: S.P. Uttam, Dept. of Electronics, Government of India, New Delhi, India
A. Guyot, Integrated Syst. Design Group, TIMA-UJF, Grenoble, France
M. Renaudin, Integrated Syst. Design Group, TIMA-UJF, Grenoble, France
B. El Hassan, Integrated Syst. Design Group, TIMA-UJF, Grenoble, France
V. Levering, Integrated Syst. Design Group, TIMA-UJF, Grenoble, France
pp. 376
Radhakrishna Nagalla, Computer and System Technology Laboratory University of NSW, Sydney, Australia
Graham Hellestrand, Computer and System Technology Laboratory University of NSW, Sydney, Australia
pp. 382
Sung-Bum Park, Dept. of Computer Science, Tokyo Institute of Technology
Takashi Nanya, Dept. of Computer Science, Tokyo Institute of Technology
pp. 389
P. Agrawal, AT&T Bell Labs., Murray Hill, NJ, USA
B. Narendran, AT&T Bell Labs., Murray Hill, NJ, USA
N. Shivakumar, AT&T Bell Labs., Murray Hill, NJ, USA
pp. 393
P.S. Dasgupta, Comput. Center, Indian Inst. of Manage., Calcutta, India
A.K. Sen, Comput. Center, Indian Inst. of Manage., Calcutta, India
S.C. Nandy, Comput. Center, Indian Inst. of Manage., Calcutta, India
B.B. Bhattacharya, Comput. Center, Indian Inst. of Manage., Calcutta, India
pp. 400
Session 23: Delay Testing: Chair: C. Shekhar, Central Electronic Eng. Research Institute, Pilani, India
M. Sivaraman, Carnegie Mellon Univ., Pittsburgh, PA, USA
A.J. Strojwas, Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 412
A.K. Majhi, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
J. Jacob, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
L.M. Patnaik, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
V.D. Agrawal, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
pp. 418
K. Heragu, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
V.D. Agrawal, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 422
M.A. Gharaybeh, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
M.L. Bushnell, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
V.D. Agrawal, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 426
Panel Discussion
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