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9th International Conference on VLSI Design: VLSI in Mobile Communication
A systolic architecture for LMS adaptive filtering with minimal adaptation delay
Bangalore, INDIA
January 03-January 06
ISBN: 0-8186-7228-5
| ASCII Text | x | ||
| S. Ramanathan, V. Visvanathan, "A systolic architecture for LMS adaptive filtering with minimal adaptation delay," VLSI Design, International Conference on, pp. 286, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996. | |||
| BibTex | x | ||
| @article{ 10.1109/ICVD.1996.489612, author = {S. Ramanathan and V. Visvanathan}, title = {A systolic architecture for LMS adaptive filtering with minimal adaptation delay}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {1996}, issn = {1063-9667}, pages = {286}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489612}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - VLSI Design, International Conference on TI - A systolic architecture for LMS adaptive filtering with minimal adaptation delay SN - 1063-9667 SP EP A1 - S. Ramanathan, A1 - V. Visvanathan, PY - 1996 KW - least mean squares methods; adaptive filters; convergence of numerical methods; systolic arrays; signal flow graphs; pipeline processing; delays; digital signal processing chips; VLSI; digital filters; systolic architecture; LMS adaptive filtering; minimal adaptation delay; LMS algorithm; convergence behaviour; function preserving transformations; signal flow graph; SFG representation; carry-save arithmetic; systolic folded pipelined architecture VL - 0 JA - VLSI Design, International Conference on ER - | |||
Existing systolic architectures for the LMS algorithm with delayed coefficient adaptation have large adaptation delay and hence degraded convergence behaviour. This paper presents a systolic architecture with minimal adaptation delay and input/output latency, thereby improving the convergence behaviour to near that of the original LMS algorithm. The architecture is synthesized by using a number of function preserving transformations on the signal flow graph representation of the delayed LMS algorithm. With the use of carry-save arithmetic, the systolic folded pipelined architecture can support very high sampling rates, limited only by the delay of a full adder.
Index Terms:
least mean squares methods; adaptive filters; convergence of numerical methods; systolic arrays; signal flow graphs; pipeline processing; delays; digital signal processing chips; VLSI; digital filters; systolic architecture; LMS adaptive filtering; minimal adaptation delay; LMS algorithm; convergence behaviour; function preserving transformations; signal flow graph; SFG representation; carry-save arithmetic; systolic folded pipelined architecture
Citation:
S. Ramanathan, V. Visvanathan, "A systolic architecture for LMS adaptive filtering with minimal adaptation delay," vlsid, pp.286, 9th International Conference on VLSI Design: VLSI in Mobile Communication, 1996
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