- V
- VLSID
- 1995
- 8th International Conference on VLSI Design
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8th International Conference on VLSI Design New Delhi, India January 04-January 07 ISBN: 0-8186-6905-5 Table of Contents
 | 1 - Routing I: Chair: S. Sahni - University of Florida - Gainesville, USA |
S.R. Danda, Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
S. Madhwapathy, Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA
N.A. Sherwani, Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA pp. 3
A. Lim, Information Technol. Inst., Singapore, Singapore
S. Sahni, Information Technol. Inst., Singapore, Singapore pp. 8
S. Das, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kanpur, India
S. Saxena, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kanpur, India pp. 13
| 2 - Hardware-Software Design/CAD: Chair: R.W. Hartenstein - University of Kaiserlautern, Germany |
R.S. Mitra, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
M.G. Qadir, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
A. Basu, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India pp. 19
R.S. Mitra, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P.S. Roop, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
A. Basu, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India pp. 30
| 3 - Sequential Automatic Test Pattern Generation: Chair: J.A. Abraham - University of Texas at Austin, USA |
J. Sienicki, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
M. Bushnell, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
P. Agrawal, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
V. Agrawal, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA pp. 36
M.K. Srinivas, CAD Lab./SERC, Indian Inst. of Sci., Bangalore, India
J. Jacob, CAD Lab./SERC, Indian Inst. of Sci., Bangalore, India
V.D. Agrawal, CAD Lab./SERC, Indian Inst. of Sci., Bangalore, India pp. 47
| 4 - Field Programmable Gate Arrays: Chair: R. Grafton -National Science Foundation, USA |
S. Kumar, Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia
K. Forward, Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia
M. Palaniswami, Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia pp. 53
S. Chattopadhyay, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
S. Roy, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P. Pal Chaudhuri, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India pp. 57
A. Pal, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
R.K. Gorai, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
V.V.S.S. Raju, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India pp. 63
M. Mehendale, Texas Instrum. (India) Pvt. Ltd., Bangalore, India pp. 69
| 5 - High-Level Synthesis: Chair: N.D. Dutt - University of California - Irvine, USA |
A. Kumar, Cadence Design Syst. (I) Pvt. Ltd., Noida, India
A. Kumar, Cadence Design Syst. (I) Pvt. Ltd., Noida, India pp. 75
J. Jain, Fujitsu Lab. of America, San Jose, CA, USA
J. Bitner, Fujitsu Lab. of America, San Jose, CA, USA
D.E. Ross, Fujitsu Lab. of America, San Jose, CA, USA pp. 81
S. Sarkar, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
A. Basu, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
A.K. Majumdar, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India pp. 87
| 6-Combinational Automatic Test Pattern Generation: Chair: D. Bhattacharya - Yale University, USA |
Xinghao Chen, CAIP Center, Rutgers Univ., Piscataway, NJ, USA pp. 99
P. Ashar, Dept. of Electr. Eng., Princeton Univ., NJ, USA
S. Malik, Dept. of Electr. Eng., Princeton Univ., NJ, USA pp. 104
S. Yadavalli, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA pp. 110
S. Seth, LSI Logic Corp., Milpitas, CA, USA pp. 116
| 7--Logic Synthesis and Retiming: Chair: A. Saldanha - Cadence Berkeley Labs, USA |
U.K. Bhattacharyya, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
I. Sen Gupta, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
S. Shyama Nath, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
P. Dutta, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India pp. 121
C. Bolchini, Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
G. Buonanno, Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
D. Sciuto, Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
R. Stefanelli, Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy pp. 125
S. Simon, Inst. for Network Theory & Circuit Design, Tech. Univ. Munchen, Germany
R. Bucher, Inst. for Network Theory & Circuit Design, Tech. Univ. Munchen, Germany
J.A. Nossek, Inst. for Network Theory & Circuit Design, Tech. Univ. Munchen, Germany pp. 130
S.T. Chakradhar, Comput. & Commun. Res. Lab., NEC Res. Inst., Princeton, NJ, USA pp. 135
| 8-VLSI Arithmetic I: Chair: M.R. Varanasi - University of South Florida, USA |
P. Patra, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.S. Fussell, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA pp. 141
A. Skaf, Integrated Syst. Design Group, TIMA Lab./INPG, Grenoble, France
A. Guyot, Integrated Syst. Design Group, TIMA Lab./INPG, Grenoble, France pp. 146
L. Penzo, Dipartimento di Elettronica, Politecnico di Milano, Italy
D. Sciuto, Dipartimento di Elettronica, Politecnico di Milano, Italy
C. Silvano, Dipartimento di Elettronica, Politecnico di Milano, Italy pp. 156
| 9 - Delay Test: Chair: T. J. Chakraborty --AT&T Bell Labs, USA |
A.K. Majhi, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
J. Jacob, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
L.M. Patnaik, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
V.D. Agrawal, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India pp. 161
K. Heragu, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
V.D. Agrawal, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
M.L. Bushnell, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA pp. 166
S.M. Nowick, Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
N.K. Jha, Dept. of Comput. Sci., Columbia Univ., New York, NY, USA pp. 171
I.P. Shaik, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
M.L. Bushnell, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA pp. 177
| 10 - Chip Design: Chair: J. Hatfield - University of Manchester Institute of Science and Technology, UK |
S. Vidya, Semicond. Complex Ltd., Bangalore, India
P. Kumar, Semicond. Complex Ltd., Bangalore, India pp. 183
| 11 - Tools and Technology Posters: Chair: G.S. Visweswaran -- IIT, India |
P. Sawhney, SGS-Thomson Microelectron., New Delhi, India
H. Rasheed, SGS-Thomson Microelectron., New Delhi, India pp. 191
V. Puvvada, Texas Instrum. (India) Pvt. Ltd., Bangalore, India
S. Potla, Texas Instrum. (India) Pvt. Ltd., Bangalore, India
T. Selvam, Texas Instrum. (India) Pvt. Ltd., Bangalore, India
P.R. Suresh, Texas Instrum. (India) Pvt. Ltd., Bangalore, India pp. 192
K.G. Praveen, Texas Instrum. (India) Pvt. Ltd., Bangalore, India
R. Ramani, Texas Instrum. (India) Pvt. Ltd., Bangalore, India pp. 193
H.A. Naseem, High Density Electron. Center, Arkansas Univ., Fayetteville, AR, USA
A.P. Malshe, High Density Electron. Center, Arkansas Univ., Fayetteville, AR, USA
R.A. Beera, High Density Electron. Center, Arkansas Univ., Fayetteville, AR, USA
M.S. Haque, High Density Electron. Center, Arkansas Univ., Fayetteville, AR, USA
W.D. Brown, High Density Electron. Center, Arkansas Univ., Fayetteville, AR, USA
L.W. Schaper, High Density Electron. Center, Arkansas Univ., Fayetteville, AR, USA pp. 194
12 - Panel: India in the VLSI World - High-Tech Innovator or Body Shop?
| 14 - Routing II: Chair: N. Sherwani - Western Michigan University, USA |
R.K. Pal, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
S.P. Pal, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
M.M. Das, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
A. Pal, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India pp. 196
R.K. Pal, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
A.K. Datta, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
S.P. Pal, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
M.M. Das, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
A. Pal, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India pp. 202
J. Khare, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
S. Mitra, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
P.K. Nag, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
U. Maly, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
R. Rutenbar, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA pp. 208
| 15 - Image Compression: Chair: S. Choudhury - IIT, New Delhi, India |
H. Sahabi, Dept. of Comput. Sci., Alberta Univ., Edmonton, Alta., Canada
A. Basu, Dept. of Comput. Sci., Alberta Univ., Edmonton, Alta., Canada
M. Fiala, Dept. of Comput. Sci., Alberta Univ., Edmonton, Alta., Canada pp. 214
M. Kovac, Fac. of Electr. Eng., Zagreb Univ., Croatia pp. 220
J. Augustine, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
Wen Feng, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
J. Jacob, Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India pp. 225
| 16 - Analog Circuit Test: Chair: A.B. Bhattacharya - IIT, New Delhi, India |
A. Devgan, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
R.A. Rohrer, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA pp. 229
N. Nagi, LogicVision, San Jose, CA, USA pp. 234
| 17 - Synthesis and Verification: Chair: S. Kumar - IIT, India |
W.L. Bradley, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
R.R. Vemuri, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA pp. 243
B.M. Subraya, Dept. of Comput. Sci. & Eng., S.J. Coll. of Eng., Mysore, India
A. Kumar, Dept. of Comput. Sci. & Eng., S.J. Coll. of Eng., Mysore, India
S. Kumar, Dept. of Comput. Sci. & Eng., S.J. Coll. of Eng., Mysore, India pp. 249
R. Kumar, Forschungszentrum Inf. Karlsruhe, Germany
T. Kropf, Forschungszentrum Inf. Karlsruhe, Germany pp. 255
| 18 - VLSI Technology/CAD: Chair: M.M. Hasan - IIT, Kanpur, India |
S.Y. Kulkarni, Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India
K.D. Patil, Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India
K.V.V. Murthy, Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India pp. 260
D.V. Das, Cadence Design Syst. (India) Pvt. Inc., Noida, India pp. 264
G.H.R. Krishna, Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India
A.K. Aditya, Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India
N.B. Chakrabarti, Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India
S. Banerjee, Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India pp. 268
| 19 - Testability: Chair: S.D. Sherlekar - IIT, Bombay, India |
C.P. Ravikumar, Dept. of Electr. Eng., Indian Inst. of Technol., Delhi, India
H. Joshi, Dept. of Electr. Eng., Indian Inst. of Technol., Delhi, India pp. 272
S.M. Aziz, Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh pp. 278
E.M. Rudnick, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA pp. 288
| 20 - Low-Power/Analog Design: Chair: P.R. Mukund - Rochester Institute of Technology, USA |
M. Borah, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
M.J. Irwin, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
R.M. Owens, Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA pp. 294
V. Catania, Istituto di Inf. e Telecommun., Catania Univ., Italy
M. Russo, Istituto di Inf. e Telecommun., Catania Univ., Italy pp. 299
S.C. Prasad, Inf. Technol. Lab., Texas Instrum. Inc., Dallas, TX, USA
K. Roy, Inf. Technol. Lab., Texas Instrum. Inc., Dallas, TX, USA pp. 305
| 21 - Array Processor Design: Chair: L.M. Patnaik - IISc, India |
G. Ascia, Istituto di Inf. e Telecommun., Catania Univ., Italy
V. Catania, Istituto di Inf. e Telecommun., Catania Univ., Italy pp. 315
L. Kurian, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
D. Brewer, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
E. John, Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA pp. 321
M.S. Gopi, Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
S. Manohar, Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India pp. 326
V. Visvanathan, Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
N. Ramanathan, Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India pp. 332
| 22 - Diagnosis and Self-Checking: Chair: B. Mitra - Texas Instruments, Bangalore, India |
Y. Gong, Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA pp. 338
S. Chattopadhyay, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kanpur, India
D.R. Chowdhuri, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kanpur, India
S. Bhattacharjee, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kanpur, India
P.P. Chaudhuri, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kanpur, India pp. 343
Yung-Yuan Chen, Dept. of Comput. Sci., Chung-Hua Polytech. Inst., Hsin-Chu, Taiwan
Ching-Hwa Cheng, Dept. of Comput. Sci., Chung-Hua Polytech. Inst., Hsin-Chu, Taiwan
Jwu-E Chen, Dept. of Comput. Sci., Chung-Hua Polytech. Inst., Hsin-Chu, Taiwan pp. 349
B.R. Kishore, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
R.A. Parekhji, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
S. Pagey, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
S.D. Sherlekar, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
G. Venkatesh, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India pp. 355
| 23 - Floorplanning and Partitioning: Chair: B.B. Bhattacharya -- Indian Statistics Institute, India |
Jin-Tai Yan, Dept. of Comput. Sci. & Inf. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Pei-Yung Hsiao, Dept. of Comput. Sci. & Inf. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan pp. 359
K. Shahookar, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
P. Mazumder, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA pp. 365
P.S. Dasgupta, Comput. Center, Indian Inst. of Manage., Calcutta, India
S. Sur-Kolay, Comput. Center, Indian Inst. of Manage., Calcutta, India pp. 370
D. Bhatia, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
J. Haralambides, Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA pp. 376
| 24 - VLSI Arithmetic II: Chair: C. Shekhar- CEERI, India |
L. Montalvo, Integrated Syst. Design Group, TIMA/INPG, Genoble, France
A. Guyot, Integrated Syst. Design Group, TIMA/INPG, Genoble, France pp. 381
A. Guyot, Integrated Syst. Design Group, TIMA/INPG, Grenoble, France
L. Montalvo, Integrated Syst. Design Group, TIMA/INPG, Grenoble, France
A. Houelle, Integrated Syst. Design Group, TIMA/INPG, Grenoble, France
H. Mehrez, Integrated Syst. Design Group, TIMA/INPG, Grenoble, France
N. Vaucher, Integrated Syst. Design Group, TIMA/INPG, Grenoble, France pp. 386
D.V. Poornaiah, Transmission R&D, Indian Telephone Ind. Ltd., Bangalore, India
P.V.A. Mohan, Transmission R&D, Indian Telephone Ind. Ltd., Bangalore, India pp. 392
H.R. Srinivas, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
K.K. Parhi, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA pp. 398
| 25 - Design and Synthesis for Testability: Chair: S. Bhawmik -AT&T Bell Labs, USA |
S.R. Das, Dept. of Electr. Eng., Ottawa Univ., Ont., Canada
H.T. Ho, Dept. of Electr. Eng., Ottawa Univ., Ont., Canada
W.-B. Jone, Dept. of Electr. Eng., Ottawa Univ., Ont., Canada
A.R. Nayak, Dept. of Electr. Eng., Ottawa Univ., Ont., Canada pp. 403
C.R. Mohan, Cadence Design Syst. (India) Pvt Ltd., Noida, India pp. 408
M. Franklin, Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
K.K. Saluja, Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
K. Kim, Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA pp. 414
J.P. Hurst, Center for Digital Syst. Res., Res. Triangle Inst., Research Triangle Park, NC, USA
A.D. Singh, Center for Digital Syst. Res., Res. Triangle Inst., Research Triangle Park, NC, USA pp. 419 Usage of this product signifies your acceptance of the Terms of Use.
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