New Delhi, India
Jan. 4, 1995 to Jan. 7, 1995
W. Amendola, Jr. , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
H.R. Srinivas , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
K.K. Parhi , Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
This paper presents the VLSI architecture and implementation of a 16/spl times/16-bit, bit-level pipelined, two's-complement binary array multiplier. This multiplier architecture employs signed-digit radix 2 carry free adders to perform multiplication. A fast conversion scheme for converting the final product, available from the multiplier array, in radix 2 signed-digit form to two's-complement binary form is employed to reduce the latency of the multiplier, furthermore, it results in savings in area in the form of reduced number or pipelining registers and half adders required for conversion, also called vector merging. This pipelined multiplier uses positive edge triggered registers and employs a single phase clocking scheme. It has been fabricated and tested to perform correctly at 50 MHz clock frequency for a supply voltage of 3.0 V. It may be noted that the speed of this multiplier is limited by 1 binary adder cell time and our test equipment imposed a limit of 50 MHz.
multiplying circuits; pipeline arithmetic; VLSI; parallel architectures; data conversion; CMOS logic circuits; CMOS multiplier; low latency vector merging; VLSI architecture; bit-level pipelined architecture; two's-complement binary array multiplier; multiplier architecture; signed-digit radix 2 adders; carry free adders; multiplication; fast conversion scheme; pipelining registers; half adders; positive edge triggered registers; single phase clocking scheme; 16 bit; 1.2 micron; 50 MHz; 3 V
W. Amendola, Jr., H.R. Srinivas, K.K. Parhi, "A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging", VLSID, 1995, VLSI Design, International Conference on, VLSI Design, International Conference on 1995, pp. 398, doi:10.1109/ICVD.1995.512146