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21st International Conference on VLSI Design (VLSI Design 2008)
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Bibliographic References
ASCII Text
BibTex
Refworks Procite/RefMan
21st International Conference on VLSI Design (VLSI Design 2008)
Hyderabad, India
January 04-January 08
ISBN: 0-7695-3083-4
Table of Contents
Introduction
Message from the General Chairs
(PDF)
pp. xiv-xv
ABSTRACT
PDF
Message from the Program Chairs
(PDF)
pp. xvi-xvii
ABSTRACT
PDF
Conference Steering Committee
(PDF)
pp. xviii
ABSTRACT
PDF
Conference Committee
(PDF)
pp. xix-xxi
ABSTRACT
PDF
Program Committee
(PDF)
pp. xxii
ABSTRACT
PDF
Reviewers
(PDF)
pp. xxiii-xxviii
ABSTRACT
PDF
Fellowships
(PDF)
pp. xxix-xxxiv
ABSTRACT
PDF
VLSI Design 2007 Awards
(PDF)
pp. xxxv
ABSTRACT
PDF
VLSI Design Conference History
(PDF)
pp. xxxvi
ABSTRACT
PDF
Embedded Systems Design Conference History
(PDF)
pp. xxxvii
ABSTRACT
PDF
Plenary Invited Keynote Speakers
(PDF)
pp. xxxviii-xxxix
ABSTRACT
PDF
Tutorials
Gateway to Chips: High Speed I/O Signalling and Interface
(PDF)
Nidhir Kumar
Senthil N. Velu
Rajan Verma
pp. 3-4
ABSTRACT
PDF
DFM / DFT / SiliconDebug / Diagnosis
(PDF)
Srikanth Venkataraman
Nagesh Tamarapalli
pp. 5-6
ABSTRACT
PDF
Oversampling Analog-to-Digital Converter Design
(PDF)
Shanthi Pavan
Nagendra Krishnapura
pp. 7
ABSTRACT
PDF
Programming and Performance Modelling of Automotive ECU Networks
(PDF)
Samarjit Chakraborty
S. Ramesh
pp. 8-9
ABSTRACT
PDF
Architecture Exploration for Low Power Design
(PDF)
Vinod Kathail
Tom Miller
pp. 10-11
ABSTRACT
PDF
Memory Design and Advanced Semiconductor Technology
(PDF)
pp. 12
ABSTRACT
PDF
Scan Delay Testing of Nanometer SoCs
(PDF)
Adit D. Singh
pp. 13
ABSTRACT
PDF
Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips
(PDF)
Fadi Kurdahi
Nikil Dutt
Ahmed Eltawil
Sani Nassif
pp. 14-15
ABSTRACT
PDF
OpenSPARC - A Scalable Chip Multi-Threading Design
(PDF)
Dwayne Lee
pp. 16
ABSTRACT
PDF
Implementing the Best Processor Cores
(PDF)
Vamsi Boppana
Rahoul Varma
S. Balajee
pp. 17-18
ABSTRACT
PDF
SESSION A1: Fault Tolerance
A Power Efficient Approach to Fault-Tolerant Register File Design
(Abstract)
Mojtaba Amiri-Kamalabad
Seyed Ghassem Miremadi
Mahdi Fazeli
pp. 21-26
ABSTRACT
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Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS
(Abstract)
Maryam Ashouei
Adit D. Singh
Abhijit Chatterjee
pp. 27-32
ABSTRACT
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Single Error Correcting Finite Field Multipliers Over GF(2
m
)
(Abstract)
Jimson Mathew
A. Costas
A.M. Jabir
H. Rahaman
D.K. Pradhan
pp. 33-38
ABSTRACT
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A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits
(Abstract)
Aditya Jagirdar
Roystein Oliveira
Tapan Jyoti Chakraborty
pp. 39-44
ABSTRACT
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Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass
(Abstract)
Kaushal R. Gandhi
Nihar R. Mahapatr
pp. 45-51
ABSTRACT
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SESSION B1: Wireless/Communication
Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding
(Abstract)
Shahid Rizwan
pp. 53-58
ABSTRACT
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Exploring the Processor and ISA Design for Wireless Sensor Network Applications
(Abstract)
Shashidhar Mysore
Banit Agrawal
Frederic T. Chong
Timothy Sherwood
pp. 59-64
ABSTRACT
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Concurrent Multi-Dimensional Adaptation for Low-Power Operation in Wireless Devices
(Abstract)
Rajarajan Senguttuvan
Shreyas Sen
Abhijit Chatterjee
pp. 65-70
ABSTRACT
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Adaptive Signal Scaling Driven Critical Path Modulation for Low Power Baseband OFDM Processors
(Abstract)
Muhammad Mudassar Nisar
Rajarajan Senguttuvan
Abhijit Chatterjee
pp. 71-76
ABSTRACT
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Fault Tolerant Dynamic Antenna Array in Smart Antenna System Using Evolved Virtual Reconfigurable Circuit
(Abstract)
D. Dhanasekaran
K. Boopathy Bagan
pp. 77-83
ABSTRACT
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SESSION C1: Embedded Systems
Multimedia Tools and Architectures for Hardware/Software Co-Simulation of Reconfigurable Systems
(Abstract)
Valery Sklyarov
Iouliia Skliarova
Bruno Pimentel
Manuel Almeid
pp. 85-90
ABSTRACT
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A Modeling of a Dynamically Reconfigurable Processor Using SystemC
(Abstract)
Junji Kitamichi
Koji Ueda
Kenichi Kurod
pp. 91-96
ABSTRACT
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A Scalable and Reconfigurable Coprocessor for Image Composition
(Abstract)
Jalaj Jain
pp. 97-102
ABSTRACT
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Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
(Abstract)
Alexandru Andrei
Petru Eles
Zebo Peng
Jakob Rosen
pp. 103-110
ABSTRACT
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An Approach to Software Performance Evaluation on Customized Embedded Processors
(Abstract)
Soumyajit Dey
Monu Kedia
Anupam Basu
pp. 111-117
ABSTRACT
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SESSION D1: Technology
Compact Modeling of Suspended Gate FET
(Abstract)
Yogesh Singh Chauhan
D. Tsamados
N. Abel?
C. Eggimann
M. Declercq
A.M. Ionescu
pp. 119-124
ABSTRACT
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Optimal Dual-V
T
Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies
(Abstract)
Aditya Bansal
Jae-Joon Kim
Keunwoo Kim
Saibal Mukhopadhyay
Ching-Te Chuang
Kaushik Roy
pp. 125-130
ABSTRACT
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Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design
(Abstract)
Amith Singhee
Jiajing Wang
Benton H. Calhoun
Rob A. Rutenbar
pp. 131-136
ABSTRACT
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NBTI Degradation: A Problem or a Scare?
(Abstract)
Kewal K. Saluja
Shriram Vijayakumar
Warin Sootkaneung
Xaingning Yang
pp. 137-142
ABSTRACT
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On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit
(Abstract)
Amlan Ghosh
Rahul M. Rao
Jae-joon Kim
Ching-Te Chuang
Richard B. Brown
pp. 143-149
ABSTRACT
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SESSION A2: Testing/DFT
On Common-Mode Skewed-Load and Broadside Tests
(Abstract)
Irith Pomeranz
Sudhakar M. Reddy
Sandip Kundu
pp. 151-156
ABSTRACT
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Testing Flash Memories for Tunnel Oxide Defects
(Abstract)
Mohammad Gh. Mohammad
Kewal K. Saluja
pp. 157-162
ABSTRACT
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On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set
(Abstract)
Hafizur Rahaman
Dipak K. Kole
Debesh K. Das
Bhargab B. Bhattacharya
pp. 163-168
ABSTRACT
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Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models
(Abstract)
Aman Kokrady
C.P. Ravikumar
Nitin Chandrachoodan
pp. 169-174
ABSTRACT
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Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths
(Abstract)
Irith Pomeranz
Sudhakar M. Reddy
pp. 175-180
ABSTRACT
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Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity
(Abstract)
Irith Pomeranz
Sudhakar M. Reddy
pp. 181-186
ABSTRACT
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A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings
(Abstract)
Nilabha Dev
Sandeep Bhatia
Subhasish Mukherjee
Sue Genova
Vinayak Kadam
pp. 187-193
ABSTRACT
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SESSION B2: Interconnects
Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling
(Abstract)
Charbel J. Akl
Magdy A. Bayoumi
pp. 195-200
ABSTRACT
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Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor
(Abstract)
Andy Lambrechts
Praveen Raghavan
Murali Jayapala
Francky Catthoor
Diederik Verkest
pp. 201-207
ABSTRACT
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Integrated TIA-Equalizer for High Speed Optical Link
(Abstract)
Saurav Bandyopadhyay
Pradip Mandal
Stephen E. Ralph
Kenneth Pedrotti
pp. 208-213
ABSTRACT
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Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance
(Abstract)
Jeff Mueller
Resve Saleh
pp. 214-219
ABSTRACT
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Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects
(Abstract)
Anish Muttreja
Prateek Mishra
Niraj K. Jha
pp. 220-227
ABSTRACT
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Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation
(Abstract)
Sampo Tuuna
Jouni Isoaho
Hannu Tenhunen
pp. 228-234
ABSTRACT
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Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design
(Abstract)
T. Venkata Kalyan
Madhu Mutyam
P. Vijaya Sankara Rao
pp. 235-241
ABSTRACT
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SESSION C2: Architecture
Dynamic Aggregation of Virtual Addresses in TLB Using TCAM Cells
(Abstract)
Rupak Samanta
Jason Surprise
Rabi Mahapatr
pp. 243-248
ABSTRACT
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Continuous Frequency Adjustment Technique Based on Dynamic Workload Prediction
(Abstract)
Hwisung Jung
Massoud Pedram
pp. 249-254
ABSTRACT
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Recursive versus Iterative Algorithms for Solving Combinatorial Search Problems in Hardware
(Abstract)
Iouliia Skliarova
Valery Sklyarov
pp. 255-260
ABSTRACT
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Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors
(Abstract)
Nagaraju Pothineni
Anshul Kumar
Kolin Paul
pp. 261-266
ABSTRACT
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An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies
(Abstract)
Terrell Bennett
Rama Sangireddy
pp. 267-272
ABSTRACT
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A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores
(Abstract)
Rajaraman Ramanarayanan
Sanu Mathew
Vasantha Erraguntla
Ram Krishnamurthy
Shay Gueron
pp. 273-278
ABSTRACT
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Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures
(Abstract)
Hui Wang
Sandeep Baldawa
Rama Sangireddy
pp. 279-285
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SESSION D2: Analog
Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples
(Abstract)
Shubhankar Basu
Balaji Kommineni
Ranga Vemuri
pp. 287-293
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An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators
(Abstract)
Jaime Ramirez-Angulo
Lalitha Mohana Kalyani-Garimella
Annajirao Garimella
Sri Raga Sudha Garimella
Antonio Lopez-Martin
Ramon Gonzalez Carvajal
pp. 294-299
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Highly Linear Wide Dynamic Swing CMOS Transconductance Multiplier Using Source-Degeneration V-I Converters
(Abstract)
Sri Raga Sudha Garimell
pp. 300-304
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Chaos-Modulated Ramp IC for EMI Reduction in PWM Buck Converters- Design and Analysis of Critical Issues
(Abstract)
Rupam Mukherjee
Amit Patra
Soumitro Banerjee
pp. 305-310
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A Fast Settling 100dB OPAMP in 180nm CMOS Process with Compensation Based Optimisation
(Abstract)
Amal Kumar Kundu
Subho Chatterjee
Tarun Kanti Bhattacharyya
pp. 311-316
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VLSI Implementation of a Digitally Tunable G
m
-C Filter with Double CMOS Pair
(Abstract)
S. Ramasamy
B. Venkataramani
K. Anbugeetha
pp. 317-322
ABSTRACT
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A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier
(Abstract)
Sounak Roy
Swapna Banerjee
pp. 323-329
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SESSION A3: Physical Design/CAD
A New Approach for Estimation of On-Resistance and Current Distribution in Power Array Layouts
(Abstract)
Jyotirmoy Ghosh
Siddhartha Mukhopadhyay
Amit Patra
Barry Culpepper
Tawen Mei
pp. 331-336
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An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning
(Abstract)
Pradeep Fernando
Srinivas Katkoori
pp. 337-342
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Fast Congestion Aware Routing for Pin Assignment
(Abstract)
Shashank Prasad
pp. 343-347
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A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions
(Abstract)
Nagaraju Pothineni
Anshul Kumar
Kolin Paul
pp. 348-353
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Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
(Abstract)
Banit Agrawal
Timothy Sherwood
Chulho Shin
Simon Yoon
pp. 354-361
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SESSION B3: Low Power - I
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
(Abstract)
Sudeep Pasricha
Young-Hwan Park
Fadi J. Kurdahi
Nikil Dutt
pp. 363-370
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Energy-Efficient, High Performance Circuits for Arithmetic Units
(Abstract)
Sundeepkumar Agarwal
Pavankumar V K
Yokesh R
pp. 371-376
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Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters
(Abstract)
Qingli Zhang
Jinxiang Wang
Yizheng Ye
pp. 377-382
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A Robust Level-Shifter Design for Adaptive Voltage Scaling
(Abstract)
Ankur Gupta
Rajat Chauhan
Vinod Menezes
Vikas Narang
Roopashree H.M.
pp. 383-388
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Low Power Hardware Architecture for VBSME Using Pixel Truncation
(Abstract)
Asral Bahari
Tughrul Arslan
Ahmet T. Erdogan
pp. 389-395
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SESSION C3: NoC/SoC
MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA Based On-Chip Networks
(Abstract)
Arun Janarthanan
Karen A. Tomko
pp. 397-402
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MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method
(Abstract)
Hao Shen
Frederic Petrot
pp. 403-408
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An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations
(Abstract)
Mahshid Sedghi
Elnaz Koopahi
Armin Alaghi
Mahmood Fathy
Zainalabedin Navabi
pp. 409-414
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High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs
(Abstract)
Somayyeh Koohi
Mohammad Mirza-Aghatabar
Shaahin Hessabi
Masoud Pedram
pp. 415-420
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PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
(Abstract)
Deepa Kannan
Aseem Gupta
Aviral Shrivastava
Nikil D. Dutt
Fadi J. Kurdahi
pp. 421-427
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SESSION D3: Nano
Single Event Upset: An Embedded Tutorial
(Abstract)
Fan Wang
Vishwani D. Agrawal
pp. 429-434
ABSTRACT
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Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture
(Abstract)
Muzaffer O. Simsir
Srihari Cadambi
Franjo Ivancic
Martin Roetteler
Niraj K. Jha
pp. 435-440
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Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits
(Abstract)
Rajat Subhra Chakraborty
Somnath Paul
Swarup Bhunia
pp. 441-446
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A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor
(Abstract)
Biswajit Ray
Santanu Mahapatra
pp. 447-452
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Design of Reversible Finite Field Arithmetic Circuits with Error Detection
(Abstract)
Jimson Mathew
Hafizur Rahaman
Babita R. Jose
Dhiraj K. Pradhan
pp. 453-459
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SESSION A4: Verification
Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers
(Abstract)
Yinlei Yu
Cameron Brien
Sharad Malik
pp. 461-468
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Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector Fitting
(Abstract)
Chi-Un Lei
Ngai Wong
pp. 469-474
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Formal Verification of a Public-Domain DDR2 Controller Design
(Abstract)
Abhishek Datta
Vigyan Singhal
pp. 475-480
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Enhanced TED: A New Data Structure for RTL Verification
(Abstract)
Pejman Lotfi-Kamran
Mehran Massoumi
Mohammad Mirzaei
Zainalabedin Navabi
pp. 481-486
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Simulation Acceleration with HW Re-Compilation Avoidance
(Abstract)
Kyuho Shim
Kesava Talupuru
Maciej Ciesielski
Seiyang Yang
pp. 487-491
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A Module Checking Based Converter Synthesis Approach for SoCs
(Abstract)
Roopak Sinha
Partha S. Roop
Samik Basu
pp. 492-501
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SESSION B4: Low Power - II
Energy Reduction in SRAM using Dynamic Voltage and Frequency Management
(Abstract)
Mohammed Shareef I
Pradeep Nair
Bharadwaj Amrutur
pp. 503-508
ABSTRACT
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Unified V
dd
- V
th
Optimization Based DVFM Controller for a Logic Block
(Abstract)
Kannan S.A.
Sreeram N.S.
Bharadwaj S. Amrutur
pp. 509-514
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Temperature and Process Variations Aware Power Gating of Functional Units
(Abstract)
Deepa Kannan
Aviral Shrivastava
Vipin Mohan
Sarvesh Bhardwaj
Sarma Vrudhula
pp. 515-520
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A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits
(Abstract)
Sriram Sambamurthy
Jacob A. Abraham
Raghuram S. Tupuri
pp. 521-526
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Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation
(Abstract)
Yuanlin Lu
Vishwani D. Agrawal
pp. 527-532
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Power Reduction of Functional Units Considering Temperature and Process Variations
(Abstract)
Deepa Kannan
Aviral Shrivastava
Sarvesh Bhardwaj
Sarma Vrudhul
pp. 533-539
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SESSION C4: Architecture/Arithmetic
Stall Power Reduction in Pipelined Architecture Processors
(Abstract)
Pejman Lotfi-Kamran
Amir-Mohammad Rahmani
Ali-Asghar Salehpour
Ali Afzali-Kusha
Zainalabedin Navabi
pp. 541-546
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A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor
(Abstract)
Sreehari Veeramachaneni
Kirthi Krishna M
Prateek G V
Subroto S
Bharat S
M.B. Srinivas
pp. 547-552
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Memory Architecture Exploration Framework for Cache Based Embedded SOC
(Abstract)
T.S. Rajesh Kumar
C.P. Ravikumar
R. Govindarajan
pp. 553-559
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A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read
(Abstract)
Satish Anand Verkila
Siva Kumar Bondada
Bharadwaj S. Amrutur
pp. 560-565
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A Novel Approach to Design BCD Adder and Carry Skip BCD Adder
(Abstract)
Ashis Kumer Biswas
Md. Mahmudul Hasan
Moshaddek Hasan
Ahsan Raja Chowdhury
Hafiz Md. Hasan Babu
pp. 566-571
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A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters
(Abstract)
Sabyasachi Das
Sunil P. Khatri
pp. 572-579
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SESSION D4: Design/MEMS/Optical
A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits
(Abstract)
Hari Vijay Venkatanarayanan
Michael Lee Bushnell
pp. 581-588
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GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes
(Abstract)
Jairam S
Navakanta Bhat
pp. 589-594
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Behavioral Modeling of a CMOS Compatible High Precision MEMS Based Electron Tunneling Accelerometer
(Abstract)
T.K. Bhattacharyya
Anandaroop Ghosh
pp. 595-600
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An Optical Reconfiguration System with Four Contexts
(Abstract)
Naoki Yamaguchi
Minoru Watanabe
pp. 601-606
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An Acceleration and Optimization Method for Optical Reconfiguration
(Abstract)
Minoru Watanabe
Naoki Yamaguchi
pp. 607-612
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0.35?, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops
(Abstract)
S. Balaji
Vinay B. Chandratre
Menka Tewani
pp. 613-619
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SESSION A5: Synthesis
Variability-Tolerant Register-Transfer Level Synthesis
(Abstract)
Anish Muttreja
Srivaths Ravi
Niraj K. Jha
pp. 621-628
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A Galois Field Based Logic Synthesis Approach with Testability
(Abstract)
J. Mathew
H. Rahaman
A.K Singh
A.M. Jabir
D.K Pradhan
pp. 629-634
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A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions
(Abstract)
Sabyasachi Das
Sunil P. Khatri
pp. 635-640
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Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis
(Abstract)
Vyas Krishnan
Srinivas Katkoori
pp. 641-646
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On the Use of Hash Tables for Efficient Analog Circuit Synthesis
(Abstract)
Almitra Pradhan
Ranga Vemuri
pp. 647-652
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An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products
(Abstract)
Sabyasachi Das
Sunil P. Khatri
pp. 653-659
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SESSION B5: Low Power - III
A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter
(Abstract)
Kaushik Bhattacharyya
Pradip Mandal
pp. 661-666
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Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization
(Abstract)
Janakiraman Viraraghavan
Bishnu Prasad Das
Bharadwaj Amrutur
pp. 667-672
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Self-Sleep Buffer for Distributed MTCMOS Design
(Abstract)
Charbel J. Akl
Magdy A. Bayoumi
pp. 673-678
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Power Management of Interactive 3D Games Using Frame Structures
(Abstract)
Yan Gu
Samarjit Chakraborty
pp. 679-684
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Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations
(Abstract)
Bishnu Prasad Das
Janakiraman V. Bharadwaj Amrutur
H.S. Jamadagni
N.V. Arvind
pp. 685-691
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SESSION C5: Security
Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm
(Abstract)
Monjur Alam
Santosh Ghosh
Dipanwita RoyChowdhury
Indranil Sengupta
pp. 693-698
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Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design
(Abstract)
Srividhya Rammohan
Vijay Sundaresan
Ranga Vemuri
pp. 699-705
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Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier
(Abstract)
Chester Rebeiro
Debdeep Mukhpodhyay
pp. 706-711
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Watermarking Video Clips with Workload Information for DVS
(Abstract)
Yicheng Huang
Samarjit Chakraborty
Ye Wang
pp. 712-717
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Throughput Efficient Parallel Implementation of SPIHT Algorithm
(Abstract)
Anilkumar V. Nandi
R.M. Banakar
pp. 718-725
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SESSION D5: Invited Special Session: Standards in EDA
Standards in EDA: An Introduction
(PDF)
Nagi Naganathan
pp. 727
ABSTRACT
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Industry Standards from Accellera
(PDF)
Shrenik Mehta
pp. 728
ABSTRACT
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IEEE Market-Oriented Standards Process and the EDA Industry
(PDF)
Dennis Brophy
pp. 729
ABSTRACT
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Design Automation Standards: The IP Providers Perspective
(PDF)
Dr. John Goodenough
pp. 730
ABSTRACT
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Driving Analog Mixed Signal Verification through Verilog-AMS
(PDF)
Sri Chandra
pp. 731
ABSTRACT
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VSI Standards, Current Status and Future Work
(PDF)
Kathy Werner
pp. 732
ABSTRACT
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Author Index
Author Index
(PDF)
pp. 733-737
ABSTRACT
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