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1997 VHDL International User's Forum (VIUF '97)
Arlington, VA
October 19-October 22
ISBN: 0-8186-8180-2
Table of Contents
Session 1: Verification
A. Peymandoust, Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Z. Navabi, Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
pp. 2
B. Kadrovach, Res. & Dev. Center, Wright-Patterson AFB, OH, USA
P. Jarusiewic, Res. & Dev. Center, Wright-Patterson AFB, OH, USA
B. Read, Res. & Dev. Center, Wright-Patterson AFB, OH, USA
R. Bishop, Res. & Dev. Center, Wright-Patterson AFB, OH, USA
L. Concha, Res. & Dev. Center, Wright-Patterson AFB, OH, USA
K. Olson, Res. & Dev. Center, Wright-Patterson AFB, OH, USA
pp. 11
S.A. Aftabjahani, Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
Z. Navabi, Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
pp. 18
Session 2: Performance Modeling
W.W. Dungan, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
R.H. Klenke, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
J.H. Aylor, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
pp. 25
T. Bautista, CAD Div., Univ. of Las Palmas de Gran Canaria, Spain
G. Marrero, CAD Div., Univ. of Las Palmas de Gran Canaria, Spain
P.P. Carballo, CAD Div., Univ. of Las Palmas de Gran Canaria, Spain
A. Nunez, CAD Div., Univ. of Las Palmas de Gran Canaria, Spain
pp. 43
Session 3: OO-VHDL
B. Djafri, LaMI Lab., Evry Univ., France
J. Benzakki, LaMI Lab., Evry Univ., France
pp. 54
P.J. Ashenden, Dept. of Comput. Sci., Adelaide Univ., SA, Australia
P.A. Wilsey, Dept. of Comput. Sci., Adelaide Univ., SA, Australia
D.E. Martin, Dept. of Comput. Sci., Adelaide Univ., SA, Australia
pp. 60
Session 4: Synthesis
Serafino Claretto, CSELT- Centro Studi e Laboratori Telecomunicazioni
Enrica Filippi, CSELT- Centro Studi e Laboratori Telecomunicazioni
Achille Montanaro, CSELT- Centro Studi e Laboratori Telecomunicazioni
Maurizio Paolini, CSELT- Centro Studi e Laboratori Telecomunicazioni
Maura Turolla., CSELT- Centro Studi e Laboratori Telecomunicazioni
pp. 88
Session 5: System Level Modeling
Perry Alexander, The University of Cincinnati
Phillip Baraona, The University of Cincinnati
pp. 96
Xavier Warzee, Thomson-CSF Optronique, France
P. Kajfasz, Thomson-CSF Optronique, France
pp. 105
T. Hadlich, Inst. of Autom., Magdeburg Univ., Germany
pp. 109
Session 6: Model Generation and Metrics
RTL Based Scan BIST (Abstract)
Subrata Roy, Lucent Technologies, Bell Laboratories
pp. 117
P.W. Salchak, Symvionics Inc., Beavercreek, OH, USA
P. Chawla, Symvionics Inc., Beavercreek, OH, USA
pp. 126
Session 7: FPGAs
Sidhartha Mohanty, Bell Laboratories, Lucent Technologies Inc.
Kapilan Maheswaran, Bell Laboratories, Lucent Technologies Inc.
Shinichiro Haruyama, Bell Laboratories, Lucent Technologies Inc.
Jiang Niu, Bell Laboratories, Lucent Technologies Inc.
pp. 135
Session 8: Legacy++
P.J. Ashenden, Dept. of Comput. Sci., Adelaide Univ., SA, Australia
P.A. Wilsey, Dept. of Comput. Sci., Adelaide Univ., SA, Australia
D.E. Martin, Dept. of Comput. Sci., Adelaide Univ., SA, Australia
pp. 170
Session R1: RASSP Model Library
J.A. DeBardelaben, Center for Signal & Image Process., Georgia Inst. of Technol., Atlanta, GA, USA
V.K. Madisetti, Center for Signal & Image Process., Georgia Inst. of Technol., Atlanta, GA, USA
A.J. Gadient, Center for Signal & Image Process., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 183
Session R2: Performance Modeling
R.H. Klenke, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
J.H. Aylor, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
B.W. Johnson, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
C.Y. Choi, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
M. Meyassed, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
R. Rao, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
W.W. Dungan, Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
pp. 190
Session 9: Test Benches and Reliability Analysis
B. Alizadeh, Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
Z. Navabi, Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
pp. 225
Session R3: Potpourri
J. Wedgwood, Lockheed Martin Adv. Technol. Labs., Camden, NJ, USA
G. Buchanan, Lockheed Martin Adv. Technol. Labs., Camden, NJ, USA
pp. 231
Session 10: Mixed Nuts
D.J. Gibson, Sch. of Design, Eng. & Comput., Bournemouth Univ., Poole, UK
M.K. Teal, Sch. of Design, Eng. & Comput., Bournemouth Univ., Poole, UK
D. Ait-Boudaoud, Sch. of Design, Eng. & Comput., Bournemouth Univ., Poole, UK
M. Winchester, Sch. of Design, Eng. & Comput., Bournemouth Univ., Poole, UK
pp. 268
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