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30th Annual Simulation Symposium (SS '97)
Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation
Atlanta, GA
April 07-April 09
ISBN: 0-8186-7934-4
ASCII Text
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Saghir A. Shaikh, Stephen A. Szygenda, "Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation," Simulation Symposium, Annual, pp. 64, 30th Annual Simulation Symposium (SS '97), 1997.
 
 
BibTex
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@article{ 10.1109/SIMSYM.1997.586486,
author = {Saghir A. Shaikh and Stephen A. Szygenda},
title = {Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation},
journal ={Simulation Symposium, Annual},
volume = {0},
year = {1997},
issn = {1080-241X},
pages = {64},
doi = {http://doi.ieeecomputersociety.org/10.1109/SIMSYM.1997.586486},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Simulation Symposium, Annual
TI - Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation
SN - 1080-241X
SP
EP
A1 - Saghir A. Shaikh,
A1 - Stephen A. Szygenda,
PY - 1997
VL - 0
JA - Simulation Symposium, Annual
ER -
 
Saghir A. Shaikh, Level One Communications, Inc.
Stephen A. Szygenda, The University of Alabama at Birmingham
This paper describes the algorithm CON2FERS, which exploits the event-level and component-level parallelisms in the concurrent technique for fault and design error simulation. This algorithm assumes asynchronous, message-based operation with NORMA, and MIMD models of programming. A design verification tool based on this algorithm is developed with object-oriented methodology using C++ and PVM. This implementation is executable on any Network of Workstations (NOW) and/or any general purpose parallel machine. The statistics on fault and error simulation performance and load balancing for some benchmark circuits are presented. Various experimental results of the effect of network and load on the performance of the CON2FERS, and the applicability of the algorithm for the hardware acceleration of CFES are also presented.
Citation:
Saghir A. Shaikh, Stephen A. Szygenda, "Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation," ss, pp.64, 30th Annual Simulation Symposium (SS '97), 1997
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