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Proceedings of the 2002 ACM/IEEE conference on Supercomputing
Pipelined Scheduling of Tiled Nested Loops onto Clusters of SMPs Using Memory Mapped Network Interfaces
Baltimore, Maryland
November 16-November 22
ISBN: 0-7695-1524-X
Maria Athanasaki, National Technical University of Athens
Aristidis Sotiropoulos, National Technical University of Athens
Georgios Tsoukalas, National Technical University of Athens
Nectarios Koziris, National Technical University of Athens
This paper describes the performance benefits attained using enhanced network interfaces to achieve low latency communication. We present a novel, pipelined scheduling approach which takes advantage of DMA communication mode, to send data to other nodes, while the CPUs are performing calculations. We also use zero-copy communication through pinned-down physical memory regions, provided by NIC's driver modules. Our testbed concerns the parallel execution of tiled nested loops onto a cluster of SMP nodes with single PCI-SCI NICs inside each node. In order to schedule tiles, we apply a hyperplane-based grouping transformation to the tiled space, so as to group together independent neighboring tiles and assign them to the same SMP node. Experimental evaluation illustrates that memory mapped NICs with enhanced communication features enable the use of a more advanced pipelined (overlapping) schedule, which considerably improves performance, compared to an ordinary blocking schedule, implemented with conventional, CPU and kernel bounded, communication primitives.
Index Terms:
memory mapped network interfaces, DMA, pipelined schedules, tile grouping, communication overlapping, SMPs
Citation:
Maria Athanasaki, Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris, "Pipelined Scheduling of Tiled Nested Loops onto Clusters of SMPs Using Memory Mapped Network Interfaces," sc, pp.23, Proceedings of the 2002 ACM/IEEE conference on Supercomputing, 2002
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