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2008
2008 20th International Symposium on Computer Architecture and High Performance Computing

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2008 20th International Symposium on Computer Architecture and High Performance Computing

October 29-November 01

ISBN: 978-0-7695-3423-7

Table of Contents

Papers

Cover Art (PDF)

pp. C4,C1

ABSTRACT

PDF

Title Page i (PDF)

pp. i

ABSTRACT

PDF

Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-vii

ABSTRACT

PDF

Message from General Chair (PDF)

pp. viii

ABSTRACT

PDF

Message from Program Committee Chairs (PDF)

pp. ix

ABSTRACT

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Conference Organizers (PDF)

pp. x

ABSTRACT

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Program Committee (PDF)

pp. xi-xii

ABSTRACT

PDF

Reviewers (PDF)

pp. xiii

ABSTRACT

PDF

Brazilian Computer Society (SBC) (PDF)

pp. xiv-xv

ABSTRACT

PDF

Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures (Abstract)

Balaji Vijayn

Dmitry V. Ponomarev

pp. 3-10

ABSTRACT

PDF

PURCHASE ARTICLE: $19

IEEE Xplore Subscribers

Aggressive Scheduling and Speculation in Multithreaded Architectures: Is it Worth its Salt? (Abstract)

Jason Loew

Dmitry Ponomarev

pp. 11-18

ABSTRACT

PDF

PURCHASE ARTICLE: $19

IEEE Xplore Subscribers

An Optimization Mechanism Intended for Two-Level Cache Hierarchy to Improve Energy and Performance Using the NSGAII Algorithm (Abstract)

Abel G. Silva-Filho

Carmelo J.A. Bastos-Filho

Davi M.A. Falc?

Filipe R. Cordeiro

Rodrigo M.C.S. Castro

pp. 19-26

ABSTRACT

PDF

PURCHASE ARTICLE: $19

IEEE Xplore Subscribers

On Simulated Annealing for the Scheduling of Parallel Applications (Abstract)

Rodrigo Fernandes de Mello

Luciano Jos? Senger

pp. 29-36

ABSTRACT

PDF

PURCHASE ARTICLE: $19

IEEE Xplore Subscribers

Controlling Processes Reassignment in BSP Applications (Abstract)

Rodrigo da Rosa Righi

pp. 37-44

PDF

PURCHASE ARTICLE: $19

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A High Performance Massively Parallel Approach for Real Time Deformable Body Physics Simulation (Abstract)

Thiago S.M.C de Farias

Mozart W.S. Almeida

Jo?o Marcelo X.N. Teixeira

Veronica Teichrieb

Judith Kelner

pp. 45-52

ABSTRACT

PDF

PURCHASE ARTICLE: $19

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A Methodology for Developing High Fidelity Communication Models for Large-Scale Applications Targeted on Multicore Systems (Abstract)

pp. 55-62

PDF

PURCHASE ARTICLE: $19

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Selection of the Register File Size and the Resource Allocation Policy on SMT Processors (Abstract)

pp. 63-70

PDF

PURCHASE ARTICLE: $19

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ORBIT: Effective Issue Queue Soft-Error Vulnerability Mitigation on Simultaneous Multithreaded Architectures Using Operand Readiness-Based Instruction Dispatch (Abstract)

Xin Fu

Tao Li

Jos? Fortes

pp. 71-78

ABSTRACT

PDF

PURCHASE ARTICLE: $19

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Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture (Abstract)

pp. 81-88

PDF

PURCHASE ARTICLE: $19

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Parallel Verified Linear System Solver for Uncertain Input Data (Abstract)

Mariana Kolberg

M?rcio Dorn

Luiz Gustavo Fernandes

Gerd Bohlender

pp. 89-96

ABSTRACT

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PURCHASE ARTICLE: $19

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Applying Virtualization and System Management in a Cluster to Implement an Automated Emulation Testbed for Grid Applications (Abstract)

pp. 97-104

PDF

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Hiding Communication Delays in Clustered Microarchitectures (Abstract)

pp. 107-114

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PURCHASE ARTICLE: $19

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Software Synthesis for Hard Real-Time Embedded Systems with Energy Constraints (Abstract)

pp. 115-122

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PURCHASE ARTICLE: $19

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A Segmented Bloom Filter Algorithm for Efficient Predictors (Abstract)

pp. 123-130

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PURCHASE ARTICLE: $19

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Measuring Operating System Overhead on CMT Processors (Abstract)

pp. 133-140

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PURCHASE ARTICLE: $19

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Aspect-Based Patterns for Grid Programming (Abstract)

Luis Daniel Benavides Navarro

pp. 141-148

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A Reconfigurable Run-Time System for Filter-Stream Applications (Abstract)

pp. 149-156

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Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design (Abstract)

James Poe

Chang-Burm Cho

Tao Li

pp. 159-166

ABSTRACT

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Performance Sensitivity of NUCA Caches to On-Chip Network Parameters (Abstract)

pp. 167-174

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A Software Transactional Memory System for an Asymmetric Processor Architecture (Abstract)

pp. 175-182

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Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory Operations (Abstract)

pp. 183-190

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Author Index (PDF)

pp. 191-192

ABSTRACT

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Roster Page (PDF)

pp. 194

ABSTRACT

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