CSDL - Proceedings S

19th International Symposium on Computer Architecture and High Performance Computing - Title (PDF)

pp. i-iii

19th International Symposium on Computer Architecture and High Performance Computing - Copyright (PDF)

pp. iv

19th International Symposium on Computer Architecture and High Performance Computing - TOC (PDF)

pp. v-viii

Introduction

Message from the General Chairs (PDF)

pp. ix

Message from the Program Committee Chairs (PDF)

pp. x

Conference Organizers (PDF)

pp. xi

Program Committee (PDF)

pp. xii-xiii

Reviewers (PDF)

pp. xiv

Brazilian Computer Society (SBC) (PDF)

pp. xv-xvii

Applications I

Multi-level Parallelism in the Computational Modeling of the Heart (Abstract)

Carolina Xavier

Rafael Sachetto

Vinicius Vieira

Rodrigo Weber dos Santos

Wagner Meira Jr.

pp. 3-10

PDF

Paulo R. P. de Souza Filho

Computational Characteristics of Production Seismic Migration and its Performance on Novel Processor Architectures (Abstract)

Jairo Panetta

Carlos A. da Cunha Filho

Fernando M. Roxo da Motta

Silvio Sinedino Pinheiro

Ivan Pedrosa Junior

Andre L. Romanelli Rosa

Luiz R. Monnerat

Leandro T. Carneiro

Carlos H.B. de Albrecht

pp. 11-18

PDF

Voice Command Recognition with Dynamic Time Warping (DTW) using Graphics Processing Units (GPU) with Compute Unified Device Architecture (CUDA) (Abstract)

Gustavo Poli

Jo?o F. Mari

Jos? Hiroki Saito

Alexandre L. M. Levada

pp. 19-25

PDF

Exploring Novel Parallelization Technologies for 3-D Imaging Applications (Abstract)

pp. 26-33

PDF

Microarchitecture

Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded Processor (Abstract)

pp. 37-44

PDF

Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional Units (Abstract)

pp. 45-53

PDF

Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications (Abstract)

Mafijul Md. Islam

pp. 54-61

PDF

Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors (Abstract)

pp. 62-68

PDF

Applications II

Performance Improvement of the Parallel Lattice Boltzmann Method Through Blocked Data Distributions (Abstract)

Claudio Schepke

Nicolas Maillard

pp. 71-78

PDF

A Scalable Parallel Deduplication Algorithm (Abstract)

pp. 79-86

PDF

A Multigrid-Schwarz Method for the Solution of Hydrodynamics and Heat Transfer Problems in Unstructured Meshes (Abstract)

pp. 87-94

PDF

Benchmarking, Performance Measurements and Analysis

Performance Evaluation of the Dual-Core Based SGI Altix 4700 (Abstract)

Rod Fatoohi

pp. 97-104

PDF

Impacts of Multiprocessor Configurations on Workloads in Bioinformatics (Abstract)

Youfeng Wu

Mauricio Breternitz Jr

Victor Ying

pp. 105-113

PDF

Application-Specific Architectures

Efficient Hardware for Modular Exponentiation Using the Sliding-Window Method with Variable-Length Partitioning (Abstract)

Nadia Nedjah

Luiza de Macedo Mourelle

pp. 117-124

PDF

Optimized Math Functions for a Fixed-Point DSP Architecture (Abstract)

Karlo Gusso Lenzi

Osamu Saotome

pp. 125-132

PDF

Grid Computing

A Component-Oriented Support for Hierarchical MPI Programming on Multi-Cluster Grid Environments (Abstract)

pp. 135-142

PDF

A Selector of Grid Resources based on the Semantic Integration of Multiple Ontologies (Abstract)

Alexandre P.C Silva

Mario A.R. Dantas

pp. 143-150

PDF

A Novel Algorithm for Indirect Reputation-Based Grid Resource Management (Abstract)

pp. 151-158

PDF

Cache and Memory Architectures

Rahul Nagpal

Y. N. Srikant

pp. 161-168

PDF

Queue Register File Optimization Algorithm for QueueCore Processor (Abstract)

pp. 169-176

PDF

Carmelo J. A. Bastos-Filho

An Intelligent Mechanism to Explore a Two-Level Cache Hierarchy Considering Energy Consumption and Time Performance (Abstract)

Abel G. Silva-Filho

pp. 177-184

PDF

A Code Compression Method to Cope with Security Hardware Overheads (Abstract)

Eduardo Wanderley Netto

pp. 185-192

PDF

Interconnection Networks, Routing, and Communication

Architectural Breakdown of End-to-End Latency in a TCP/IP Network (Abstract)

Steen Larsen

Parthasarathy Sarangam

Ram Huggahalli

pp. 195-202

PDF

Guilherme de Melo Baptista Domingues

Performance Analysis and Linear Optimization Modeling of All-to-all Collective Communication Algorithms (Abstract)

Hyacinthe Nzigou Mamadou

Takeshi Nanri

Kazuaki Murakami

pp. 203-210

PDF

Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP) (Abstract)

pp. 211-218

PDF

Tools for Parallel and Distributed Programming

Node Level Primitives for Parallel Exact Inference (Abstract)

Yinglong Xia

Viktor K. Prasanna

pp. 221-228

PDF

Fault-tolerance in filter-labeled-stream applications (Abstract)

pp. 229-236

PDF

Francisco Heron de Carvalho-Junior

High-Level Service Connectors for Component-Based High Performance Computing (Abstract)

Ricardo Cordeiro Corrêa

Gisele Azevedo Araújo

Jefferson Carvalho Silva

Rafael Dueire Lins

pp. 237-244

PDF

Load Balancing and Scheduling

On-line Scheduling of MPI-2 Programs with Hierarchical Work Stealing (Abstract)

Philippe O. A. Navaux

pp. 247-254

PDF

Exigency-based real-time scheduling policy to provide absolute QoS for web services (Abstract)

Lucas S. Casagrande

Rodrigo F. de Mello

Ricardo Bertagna

José A. Andrade Filho

Francisco J. Monaco

pp. 255-262

PDF

DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems (Abstract)

pp. 263-270

PDF

Marluce Rodrigues Pereira

Automatic Constraint Partitioning to Speed Up CLP Execution (Abstract)

Patrícia Kayser Vargas

Maria Clícia Stelling de Castro

Felipe M. G. França

Inâs de Castro Dutra

pp. 271-278

PDF

Author Index

Author Index (PDF)

pp. 279