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SBAC-PAD
2002
14th Symposium on Computer Architecture and High Performance Computing (SCAB-PAD'02)
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14th Symposium on Computer Architecture and High Performance Computing (SCAB-PAD'02)
Vit?ria, ES, Brazil
October 28-October 30
ISBN: 0-7695-1772-2
Table of Contents
General Chair's Message
(PDF)
pp. viii
ABSTRACT
PDF
Program Chair's Message
(PDF)
pp. ix
ABSTRACT
PDF
Committees
(PDF)
pp. x
ABSTRACT
PDF
Reviewers
(PDF)
pp. xii
ABSTRACT
PDF
Brazilian Computer Society (SBC)
(PDF)
pp. xiii
ABSTRACT
PDF
Invited Paper
Infrastructure, Requirements and Applications for e-Science
(Abstract)
Ron Perrott
pp. 0003
ABSTRACT
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PURCHASE ARTICLE: $19
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Session 1: Application-Specific Architectures
Instruction Set Extension for Long Integer Modulo Arithmetic on RISC-Based Smart Cards
(Abstract)
J. Großschädl
pp. 0013
ABSTRACT
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Interactive Ray Tracing Using a SIMD Reconfigurable Architecture
(Abstract)
M. Anid
N. Bagherzadeh
N. Tabrizi
H. Du
M. Sanchez-Elez M.
pp. 0020
ABSTRACT
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Architecture of Oscillatory Neural Network for Image Segmentation
(Abstract)
D. Fernandes
J. Stedile
P. Navaux
pp. 0029
ABSTRACT
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Session 2: High Performance Applications
Simulating Semiconductor Spectra Emissions in a PC Cluster
(Abstract)
G. Sipahi
G. Travieso
pp. 0039
ABSTRACT
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Improving the Communication Network of a Cluster of PC's to Solve Implicit CFD Problems
(Abstract)
R. Silva
M. Rivello
R. Amorim
pp. 0044
ABSTRACT
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Parallel Boundary Elements Using Lapack and ScaLapack
(Abstract)
M. Cunha
J. Telles
A. Coutinho
pp. 0051
ABSTRACT
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Session 3: Parallel and Distributed Programming: Algorithms and Tools
Efficient Cyclic Weighted Reference Counting
(Abstract)
R. Lins
pp. 0061
ABSTRACT
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Generating Java Code for TINA Systems
(Abstract)
R. Guimarães
W. da Cunha Borelli
pp. 0068
ABSTRACT
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A Parallel Approximation Hitting Set Algorithm for Gene Expression Analysis
(Abstract)
D. Ruchkys
S. Song
pp. 0075
ABSTRACT
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Implementing Declarative Parallel Bottom-Avoiding Choice
(Abstract)
A. Du Bois
R. Pointon
H.-W. Loidl
P. Trinder
pp. 0082
ABSTRACT
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Session 4: Cache and Memory Architectures
An Advanced Filtering TLB for Low Power Consumption
(Abstract)
J.-H. Choi
J.-H. Lee
G.-H. Park
S.-D. Kim
pp. 0093
ABSTRACT
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Minimally-Skewed-Associative Caches
(Abstract)
A. Djordjalian
pp. 0100
ABSTRACT
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Simulating L3 Caches in Real Time Using Hardware Accelerated Cache Simulation (HACS): A Case Study with SPECint 2000
(Abstract)
M. Watson
J. Flanagan
pp. 0108
ABSTRACT
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Session 5: Grid, Multimedia, and Cluster-Based Computing
GloVE: A Distributed Environment for Low Cost Scalable VoD Systems
(Abstract)
L. Pinho
C. Amorim
E. Ishikawa
pp. 0117
ABSTRACT
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A Framework for Exploiting Adaptation in Highly Heterogeneous Distributed Processing
(Abstract)
A. Yamin
J. Barbosa
I. Augustin
L. da Silva
R. Real
C. Geyer
G. Cavalheiro
pp. 0125
ABSTRACT
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Cluster-Based Static Scheduling: Theory and Practice
(Abstract)
C. Boeres
V. Rebello
pp. 0133
ABSTRACT
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The Virtual Cluster: A Dynamic Environment for Exploitation of Idle Network Resources
(Abstract)
C. de Rose
F. Blanco
N. Maillard
K. Saikoski
R. Novaes
O. Richard
B. Richard
pp. 0141
ABSTRACT
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Session 6: Distributed Shared Memory
Design and Evaluation of Data Access Prediction Strategies in SDSM Systems
(Abstract)
E. Pineschi
M. de Castro
C. Amorim
pp. 0151
ABSTRACT
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Distributed Shared Memory in Kernel Mode
(Abstract)
T. Trevisan
V. Costa
L. Whately
C. Amorim
pp. 0159
ABSTRACT
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Session 7: Processor Architecture
Instruction Usage and the Memory Gap Problem
(Abstract)
E. Fernandes
V. Barbosa
F. Ramos
pp. 0169
ABSTRACT
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T&D-Bench: An Environment for Modeling and Simulating Complex Processor Architectures
(Abstract)
D. Becker
J. Otero
F. Wagner
pp. 0176
ABSTRACT
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Exploiting Loop-Level Parallelism with the Shift Architecture
(Abstract)
C. Lima
T. Nakamura
pp. 0184
ABSTRACT
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Session 8: Performance Analysis and Tools
An Evaluation of Processor Co-allocation for Different System Configurations and Job Structures
(Abstract)
A. Bucur
D. Epema
pp. 0195
ABSTRACT
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Performance Analysis of Parallel Programs Using Prober as a Single Aid Tool
(Abstract)
L. Góes
L. Ramos
C. Martins
pp. 0204
ABSTRACT
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Performance and Scalability Measurement of COTS EJB Technology
(Abstract)
J. Liu
pp. 0212
ABSTRACT
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Author Index
(PDF)
pp. 0221
ABSTRACT
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