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20th IEEE Real-Time Systems Symposium (RTSS'99)
A Framework for Scheduler Synthesis
Phoenix, Arizona
December 01-December 03
ISBN: 0-7695-0475-2
K. Altisen, Verimag Center
G. Gößler, Verimag Center
A. Pnueli, Verimag Center
J. Sifakis, Verimag Center
S. Tripakis, Verimag Center
S. Yovine, Verimag Center
In this paper we present a framework integrating specification and scheduler generation for real-time systems. In a first step, the system, which can include arbitrarily designed tasks (cyclic or sporadic, with or without precedence constraints, any number of resources and CPUs) is specified as a timed Petri-net. In a second step, our tool generates the most general non-preemptive online scheduler for the specification, using a controller synthesis technique.
Index Terms:
real-time systems, scheduler synthesis, timed petri nets, timed automata
Citation:
K. Altisen, G. Gößler, A. Pnueli, J. Sifakis, S. Tripakis, S. Yovine, "A Framework for Scheduler Synthesis," rtss, pp.154, 20th IEEE Real-Time Systems Symposium (RTSS'99), 1999
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