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Fourth International Workshop on Real-Time Computing Systems and Applications (RTCSA'97)
Improving processor utilization with a task classification model based application specific hard real-time architecture
Taipei, TAIWAN
October 27-October 29
ISBN: 0-8186-8073-3
| ASCII Text | x | ||
| G. Farber, F. Fischer, T. Kolloch, A. Muth, "Improving processor utilization with a task classification model based application specific hard real-time architecture," 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, pp. 276, Fourth International Workshop on Real-Time Computing Systems and Applications (RTCSA'97), 1997. | |||
| BibTex | x | ||
| @article{ 10.1109/RTCSA.1997.629234, author = {G. Farber and F. Fischer and T. Kolloch and A. Muth}, title = {Improving processor utilization with a task classification model based application specific hard real-time architecture}, journal ={2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications}, volume = {0}, year = {1997}, isbn = {0-8186-8073-3}, pages = {276}, doi = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.1997.629234}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications TI - Improving processor utilization with a task classification model based application specific hard real-time architecture SN - 0-8186-8073-3 SP EP A1 - G. Farber, A1 - F. Fischer, A1 - T. Kolloch, A1 - A. Muth, PY - 1997 KW - software prototyping; processor utilization; task classification model; application specific hard real-time architecture; microprocessors; caches; pipelines; execution times; hard real time systems; real-time architecture; target architecture framework; tightly coupled heterogeneous multiprocessor system; templates; schedulability analysis; rapid prototyping platform VL - 0 JA - 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications ER - | |||
Modern microprocessors with caches and pipelines show increasing performance, but at the price of a decreasing predictability of execution times. The design of hard real time systems however has to be based on worst case considerations. Consequently, real-time systems are generally oversized and fail to profit of developments in the standard processor field. This paper presents an approach where real-time systems are analyzed and built according to a task classification model. Each class of tasks corresponds to a type of processor best suited in terms of performance and deterministic execution times. The resulting target architecture framework is a tightly coupled heterogeneous multiprocessor system based on templates using off-the-shelf components. The described real-time system design process includes a schedulability analysis method that supports the partitioning and allocation process and provides the necessary real-time guarantees. The result is a event-driven hard real-time system with improved processor utilization that will provably meet all its deadlines. A rapid prototyping platform implementing this concept is presented as well as application examples.
Index Terms:
software prototyping; processor utilization; task classification model; application specific hard real-time architecture; microprocessors; caches; pipelines; execution times; hard real time systems; real-time architecture; target architecture framework; tightly coupled heterogeneous multiprocessor system; templates; schedulability analysis; rapid prototyping platform
Citation:
G. Farber, F. Fischer, T. Kolloch, A. Muth, "Improving processor utilization with a task classification model based application specific hard real-time architecture," rtcsa, pp.276, Fourth International Workshop on Real-Time Computing Systems and Applications (RTCSA'97), 1997
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