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2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)
Mapping a multi-rate synchronous language to a many-core processor
Philadelphia, PA, USA USA
April 09-April 11
ISBN: 978-1-4799-0186-9
Wolfgang Puffitsch, ONERA - DTIM, Toulouse, France
Eric Noulard, ONERA - DTIM, Toulouse, France
Claire Pagetti, ONERA - DTIM, Toulouse, France
This paper describes an end-to-end framework for the design and the implementation of real-time systems on a many-core architecture. The system, described in the multi-rate synchronous language Prelude, is translated into a set of communicating periodic tasks. We present a first heuristic to compute a partitioning of this task set that takes into account the specifics of the underlying platform, the Intel Single-chip Cloud Computer (SCC). In particular, the heuristic considers the communication between tasks. Furthermore, we provide a schedulability analysis that is used to validate the partitioning. We successfully apply the heuristic to several realistic use cases to evaluate the effectiveness of the proposed framework. For executing the task set, we have developed a run-time environment based on a bare-metal library that allows partitioned non-preemptive earliest deadline first (EDF) scheduling and manages the communication between tasks via the message passing mechanisms provided by the Intel SCC. The evaluation shows that the run-time overheads introduced by the framework are reasonably low.
Index Terms:
Many-core architecture,Real time systems,Multi-rate synchronous language
Citation:
Wolfgang Puffitsch, Eric Noulard, Claire Pagetti, "Mapping a multi-rate synchronous language to a many-core processor," rtas, pp.293-302, 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2013
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