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Philadelphia, PA, USA USA
Apr. 9, 2013 to Apr. 11, 2013
ISBN: 978-1-4799-0186-9
pp: 273-282
Semeen Rehman , Department of Informatics, Karlsruhe Institute of Technology (KIT), Germany
Anas Toma , Department of Informatics, Karlsruhe Institute of Technology (KIT), Germany
Florian Kriebel , Department of Informatics, Karlsruhe Institute of Technology (KIT), Germany
Muhammad Shafique , Department of Informatics, Karlsruhe Institute of Technology (KIT), Germany
Jian-Jia Chen , Department of Informatics, Karlsruhe Institute of Technology (KIT), Germany
Jorg Henkel , Department of Informatics, Karlsruhe Institute of Technology (KIT), Germany
ABSTRACT
To enable reliable embedded systems, it is imperative to leverage the compiler and system software for joint optimization of functional correctness, i.e., vulnerability indexes, and timing correctness, i.e., the deadline misses. This paper considers the optimization of the Reliability-Timing (RT) penalty, defined as a linear combination of the vulnerability indexes (reliability penalties) and the deadline misses. We propose a multi-layer approach to achieve reliable code generation and execution at compilation and system software layers for embedded systems. This is enabled by the concept of generating multiple versions, for given application functions, with diverse performance and reliability tradeoffs, by exploiting different reliability-guided compilation options. Based on the reliability and execution time profiling of these versions, our reliability-driven system software employs dynamic version selections to dynamically select a suitable version of a function according to the execution behavior of the previous functions. Specifically, our scheme builds a schedule table offline to optimize the RT penalty, and uses this table at run time to select suitable versions for the subsequent functions properly. A complex real-world application of “secure video and audio processing” composed of various functions is evaluated for reliable code generation and execution. The reliability analysis and evaluation is performed on a reliability-aware processor simulator.
CITATION
Semeen Rehman, Anas Toma, Florian Kriebel, Muhammad Shafique, Jian-Jia Chen, Jorg Henkel, "Reliable code generation and execution on unreliable hardware under joint functional and timing reliability considerations", RTAS, 2013, 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS) 2013, pp. 273-282, doi:10.1109/RTAS.2013.6531099
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