CSDL Home R RTAS 2013 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)
Philadelphia, PA, USA USA
Apr. 9, 2013 to Apr. 11, 2013
Tullio Vardanega , Department of Mathematics, University of Padua, Italy
Truly incremental development is a holy grail of verification-intensive software industry. All factors that threaten it should be removed. Cache memories have an intrinsically jittery timing behavior. The WCET variability that this causes wrecks incrementality. This hazard occurs as the WCET bounds of a software system can only be safely determined when its final memory map is known, which only happens at the end of development. Interestingly, the memory layout optimization techniques, originally devised to optimize average- or worst-case cache response time, open some avenue to control the innate dependence of cache behavior on memory layout. The state-of-the-art approaches, though effective to their own goal, are onerous to use and intrinsically iterative, hence arch-enemy of incrementality. As such they do not lend themselves to effective application in real-world industrial development. In this paper, looking at instruction caches, we describe a novel procedure positioning technique that makes it possible to control the memory layout across incremental software releases. Experimental evidence confirms that our approach facilitates early reasoning on the timing behaviour of system increments and also improves cache performance.
WCET, Caches, Incremental Development, Optimization, Memory Layout
Tullio Vardanega, "A rapid cache-aware procedure positioning optimization to favor incremental development", RTAS, 2013, 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS) 2013, pp. 107-116, doi:10.1109/RTAS.2013.6531084