Cover Art

doi:10.1109/RSP.2009.39

R
RSP
2009
2009 IEEE/IFIP International Symposium on Rapid System Prototyping

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2009 IEEE/IFIP International Symposium on Rapid System Prototyping

Paris, France

June 23-June 26

ISBN: 978-0-7695-3690-3

Table of Contents

Papers

Cover Art (PDF)

pp. C4,C1

ABSTRACT

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Title Page i (PDF)

pp. i

ABSTRACT

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Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-vii

ABSTRACT

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Message from General Chairs (PDF)

pp. viii

ABSTRACT

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Message from Program Chairs (PDF)

pp. ix-x

ABSTRACT

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Message from the Organizing Chair (PDF)

pp. xi

ABSTRACT

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Conference Committees (PDF)

pp. xii

ABSTRACT

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An Experimental Model-Based Rapid Prototyping Environment for High-Confidence Embedded Software (Abstract)

Joseph Porter

Peter Volgyesi

Nicholas Kottenstette

pp. 3-10

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WoLFram- A Word Level Framework for Formal Verification (Abstract)

pp. 11-17

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Rapid-Prototyping of Adaptive Component-Based Systems Using Runtime Aspectual Interactions (Abstract)

pp. 18-25

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Adapting Models to Model Checkers, A Case Study : Analysing AADL Using Time or Colored Petri Nets (Abstract)

pp. 26-33

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A Formal Method for Rapid SoC Prototyping (Abstract)

Christos Pavlatos

Alexandros C. Dimopoulos

George Papakonstantinou

pp. 34-37

ABSTRACT

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A Flexible High Throughput FPGA Based Prototype Platform for RW Channel Development (Abstract)

Ly Dang

pp. 41-47

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Synthesis of Communication Mechanisms for Multi-tile Systems Based on Heterogeneous Multi-processor System-On-Chips (Abstract)

Alexandre Chagoya-Garzon

Pier Stanislao Paolucci

pp. 48-54

ABSTRACT

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Efficient Heuristics for Minimizing Communication Overhead in NoC-based Heterogeneous MPSoC Platforms (Abstract)

Amit Kumar Singh

Wu Jigang

Alok Prakash

Thambipillai Srikanthan

pp. 55-60

ABSTRACT

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Communication-Aware Hierarchical Online-Placement in Heterogeneous Reconfigurable Systems (Abstract)

pp. 61-67

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Testing of an FPGA Based C2X-Communication Prototype with a Model Based Traffic Generation (Abstract)

pp. 68-71

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Operating System Support for Difference-Based Partial Hardware Reconfiguration (Abstract)

Tiago de Albuquerque Reis

Antônio Augusto Fröhlich

pp. 75-80

ABSTRACT

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A Methodology for Rapid Optimization of HandelC Specifications (Abstract)

Joey C. Libby

Kenneth B. Kent

pp. 81-87

ABSTRACT

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High-Level System Modeling for Rapid HW/SW Architecture Exploration (Abstract)

pp. 88-94

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Rapid Prototyping Projection Algorithms with FPGA Technology (Abstract)

pp. 95-101

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Automatic Code Generation from Real-Time Systems Specifications (Abstract)

pp. 102-105

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Generating an Efficient Instruction Set Simulator from a Complete Property Suite (Abstract)

pp. 109-115

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A Generic Instruction Set Simulator API for Timed and Untimed Simulation and Debug of MP2-SoCs (Abstract)

Nicolas Pouillon

Alexandre Becoulet

Aline Vieira de Mello

Francois Pecheux

Alain Greiner

pp. 116-122

ABSTRACT

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Configuration Measurement for FPGA-based Trusted Platforms (Abstract)

pp. 123-129

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Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer (Abstract)

pp. 130-133

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High-Performance Buffer Mapping to Exploit DRAM Concurrency in Multiprocessor DSP Systems (Abstract)

Dongwon Lee

Shuvra S. Bhattacharyya

Wayne Wolf

pp. 137-144

ABSTRACT

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Area-Time Estimation of Controller for Porting C-Based Functions onto FPGA (Abstract)

Lieu My Chuong

Siew-Kei Lam

Thambipillai Srikanthan

pp. 145-151

ABSTRACT

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Instruction Cache Tuning for Embedded Multitasking Applications (Abstract)

Santanu Kumar Dash

Thambipillai Srikanthan

pp. 152-158

ABSTRACT

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Efficient Data Access Management for FPGA-Based Image Processing SoCs (Abstract)

pp. 159-165

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Design and Implementation of an UWB Digital Transmitter Based on the Multiband OFDM Physical Layer Proposal (Abstract)

Platsis Michalis

Papaefstathiou Ioannis

Meintanis Dimitrios

pp. 166-169

ABSTRACT

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Physical Layer Extraction of FlexRay Configuration Parameters (Abstract)

pp. 173-180

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An Interactive Approach to Timing Accurate PCI-X Simulation (Abstract)

pp. 181-187

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An Approach to Supply Simulations of the Functional Environment of ECUs for Hardware-in-the-Loop Test Systems Based on EE-architectures Conform to AUTOSAR (Abstract)

Martin Hillenbrand

K.D. Müller-Glaser

pp. 188-195

ABSTRACT

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FPGA-based Radar Signal Processing for Automotive Driver Assistance System (Abstract)

pp. 196-199

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Author Index (PDF)

pp. 200-201

ABSTRACT

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Publisher's Information (PDF)

pp. 202

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