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16th IEEE International Workshop on Rapid System Prototyping (RSP'05)
Heterogeneous Modelling of an Optical Network-on-Chip with SystemC
Montreal, Canada
June 08-June 10
ISBN: 0-7695-2361-7
Matthieu Bri?re, Laboratory of Electronics Optoelectronics and Microsystems - Ecole Centrale de Lyon
Emmanuel Drouard, Laboratory of Electronics Optoelectronics and Microsystems - Ecole Centrale de Lyon
Fabien Mieyeville, Laboratory of Electronics Optoelectronics and Microsystems - Ecole Centrale de Lyon
David Navarro, Laboratory of Electronics Optoelectronics and Microsystems - Ecole Centrale de Lyon
Ian O?Connor, Laboratory of Electronics Optoelectronics and Microsystems - Ecole Centrale de Lyon
Fr?d?ric Gaffiot, Laboratory of Electronics Optoelectronics and Microsystems - Ecole Centrale de Lyon
This paper presents a heterogeneous model of an Optical Network-on Chip (ONoC). An ONoC is an optical interconnect architecture integrated on a System-on-Chip, and is intended to replace traditional electrical Networks-on- Chip (NoC) to overcome their future bandwidth limitations. To evaluate the advantages of a technological implementation of an ONoC, it is necessary to model its behavior and to realize a virtual prototype to estimate its power, latency, area, bandwidth, and subsequently to compare these parameters with the performance of a classical NoC. To model the ONoC at a high abstraction level, a rich system-level design language is used (SystemC). A bottom-up approach is used for the high level ONoC model description, and the performance values used at this level are extracted from the physical level with specific tools and models.
Citation:
Matthieu Bri?re, Emmanuel Drouard, Fabien Mieyeville, David Navarro, Ian O?Connor, Fr?d?ric Gaffiot, "Heterogeneous Modelling of an Optical Network-on-Chip with SystemC," rsp, pp.10-16, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05), 2005
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