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Sixth IEEE International Workshop on Rapid System Prototyping (RSP'95)
Chapel Hill, North Carolina
June 07-June 09
ISBN: 0-8186-7100-9
Table of Contents
Session 1: Keynote Presentation
Session 2: Trade-Off Between Hardware and Software Implementations
A. Kalavade, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
E.A. Lee, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 12
L.P.M. Benders, Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
pp. 26
Session 3: Prototyping Environments with Target Platform Consisting of Processors and FPGAs
M. Ade, ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
R. Lauwereins, ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
J.A. Peperstraete, ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
pp. 40
H.-J. Herpel, Tech. Hochschule Darmstadt, Germany
M. Glesner, Tech. Hochschule Darmstadt, Germany
H. Eggert, Tech. Hochschule Darmstadt, Germany
W. Suss, Tech. Hochschule Darmstadt, Germany
M. Georges-Schleuter, Tech. Hochschule Darmstadt, Germany
W. Jakob, Tech. Hochschule Darmstadt, Germany
pp. 48
T. Benner, Inst. fur Datenverarbeitungsanlagen, Tech. Univ. Braunschweig, Germany
R. Ernst, Inst. fur Datenverarbeitungsanlagen, Tech. Univ. Braunschweig, Germany
I. Konenkamp, Inst. fur Datenverarbeitungsanlagen, Tech. Univ. Braunschweig, Germany
P. Schuler, Inst. fur Datenverarbeitungsanlagen, Tech. Univ. Braunschweig, Germany
H.-C. Schaub, Inst. fur Datenverarbeitungsanlagen, Tech. Univ. Braunschweig, Germany
pp. 54
Session 4: Industrial Applications I
M. Romdhani, CNRS, Univ. Joseph Fourier, Grenoble, France
A. Jeffroy, CNRS, Univ. Joseph Fourier, Grenoble, France
P. de Chazelles, CNRS, Univ. Joseph Fourier, Grenoble, France
A.E.K. Sahraoui, CNRS, Univ. Joseph Fourier, Grenoble, France
A.A. Jerraya, CNRS, Univ. Joseph Fourier, Grenoble, France
pp. 62
D. Herold, Woods Hole Oceanogr. Instn., MA, USA
P. Fiore, Woods Hole Oceanogr. Instn., MA, USA
E. Will, Woods Hole Oceanogr. Instn., MA, USA
G. Edelson, Woods Hole Oceanogr. Instn., MA, USA
pp. 68
S. Fink, Logic Syst. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
E. Sanchez, Logic Syst. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
pp. 75
Session 5: Industrial Applications II
I.C. Kralijic, Lab. Syst. de Perception, Etablissement Tech. Central de l'Armement, Arcueil, France
G.M. Quenot, Lab. Syst. de Perception, Etablissement Tech. Central de l'Armement, Arcueil, France
B. Zavidovique, Lab. Syst. de Perception, Etablissement Tech. Central de l'Armement, Arcueil, France
pp. 97
O. Rasmont, Fac. des Polytech., Mons Univ., Belgium
J. Koulischer, Fac. des Polytech., Mons Univ., Belgium
J. Schaumont, Fac. des Polytech., Mons Univ., Belgium
R. Crappe, Fac. des Polytech., Mons Univ., Belgium
pp. 104
C.W. Chau, City Univ. of Hong Kong, Hong Kong
S. Kwong, City Univ. of Hong Kong, Hong Kong
K.F. Man, City Univ. of Hong Kong, Hong Kong
N.A. Halang, City Univ. of Hong Kong, Hong Kong
A.D. Stoyenko, City Univ. of Hong Kong, Hong Kong
pp. 110
Session 6: Prototyping of Software I
A. Jirachiefpattana, Dept. of Comput. Sci. & Eng., La Trobe Univ., Bundoora, Vic., Australia
R. Lai, Dept. of Comput. Sci. & Eng., La Trobe Univ., Bundoora, Vic., Australia
pp. 118
J.L. Sidoran, Rome Lab., Griffiss AFB, NY, USA
C.L. Burns, Rome Lab., Griffiss AFB, NY, USA
S. Maethner, Rome Lab., Griffiss AFB, NY, USA
D. Spencer, Rome Lab., Griffiss AFB, NY, USA
H. Bond, Rome Lab., Griffiss AFB, NY, USA
pp. 125
F. Kordon, Lab. MASI, Univ. Pierre et Marie Curie, Paris, France
W.E. Kaim, Lab. MASI, Univ. Pierre et Marie Curie, Paris, France
pp. 131
Session 7: Prototyping of Software II
T. Antonakopoulos, Dept. of Electr. Eng., Patras Univ., Greece
K. Agavanakis, Dept. of Electr. Eng., Patras Univ., Greece
V. Makios, Dept. of Electr. Eng., Patras Univ., Greece
pp. 140
Session 8: VHDL Simulation
S. Olcoz, Dept. of Design Technol., TGI S.A., Madrid, Spain
L. Entrena, Dept. of Design Technol., TGI S.A., Madrid, Spain
L. Berrojo, Dept. of Design Technol., TGI S.A., Madrid, Spain
pp. 161
J.D.S. Babcock, Dept. of Electr. Eng., Duke Univ., Durham, NC, USA
A. Dollas, Dept. of Electr. Eng., Duke Univ., Durham, NC, USA
pp. 168
K.A. Kwiat, Rome Lab., Griffiss AFB, NY, USA
W.H. Debany, Jr., Rome Lab., Griffiss AFB, NY, USA
S. Hariri, Rome Lab., Griffiss AFB, NY, USA
pp. 174
Session 9: Prototyping Environments with Target IPlatform Consisting of Processors
M.S. Khan, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander, Jr., Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 187
S.S. Bhattacharyya, Hitachi America Ltd., Brisbane, CA, USA
P.K. Murthy, Hitachi America Ltd., Brisbane, CA, USA
E.A. Lee, Hitachi America Ltd., Brisbane, CA, USA
pp. 194
G.S. Manku, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
A. Kumar, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
S. Kumar, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
pp. 201
Session 10: Prototyping Environments with Target Platform Consisting of FPGAs
A. Hedberg, Div. of Comput. Sci., Lulea Univ. of Technol., Sweden
H. Jacobson, Div. of Comput. Sci., Lulea Univ. of Technol., Sweden
M. Einarsson, Div. of Comput. Sci., Lulea Univ. of Technol., Sweden
G. Jennings, Div. of Comput. Sci., Lulea Univ. of Technol., Sweden
pp. 217
H.N. Nguyen, Hardware Dev. Paris-Angers, Les Clayes-sous-Bois, France
Y. Gressus, Hardware Dev. Paris-Angers, Les Clayes-sous-Bois, France
M. D'Hoe, Hardware Dev. Paris-Angers, Les Clayes-sous-Bois, France
pp. 223
E. do Valle Simoes, Federal Univ. of Rio Grande do Sul, Porto Algere, Brazil
D.A.C. Barone, Federal Univ. of Rio Grande do Sul, Porto Algere, Brazil
pp. 226
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