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2010 International Conference on Reconfigurable Computing and FPGAs
Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism
Cancun, Quintana Roo Mexico
December 13-December 15
ISBN: 978-0-7695-4314-7
| ASCII Text | x | ||
| Gabriel Marchesan Almeida, Sameer Varyani, Rémi Busseuil, Nicolas Hebert, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert, "Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism," Reconfigurable Computing and FPGAs, International Conference on, pp. 382-387, 2010 International Conference on Reconfigurable Computing and FPGAs, 2010. | |||
| BibTex | x | ||
| @article{ 10.1109/ReConFig.2010.17, author = {Gabriel Marchesan Almeida and Sameer Varyani and Rémi Busseuil and Nicolas Hebert and Gilles Sassatelli and Pascal Benoit and Lionel Torres and Michel Robert}, title = {Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism}, journal ={Reconfigurable Computing and FPGAs, International Conference on}, volume = {0}, year = {2010}, isbn = {978-0-7695-4314-7}, pages = {382-387}, doi = {http://doi.ieeecomputersociety.org/10.1109/ReConFig.2010.17}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Reconfigurable Computing and FPGAs, International Conference on TI - Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism SN - 978-0-7695-4314-7 SP382 EP387 A1 - Gabriel Marchesan Almeida, A1 - Sameer Varyani, A1 - Rémi Busseuil, A1 - Nicolas Hebert, A1 - Gilles Sassatelli, A1 - Pascal Benoit, A1 - Lionel Torres, A1 - Michel Robert, PY - 2010 KW - MPSoC KW - homogeneous KW - PID KW - adaptive KW - NoC KW - distributed memory KW - RTOS VL - 0 JA - Reconfigurable Computing and FPGAs, International Conference on ER - | |||
In this paper we propose a strategy for better exploiting Multi-Processor Systems-on-Chip resources utilization by means of using a control-loop feedback mechanism. We apply the proposed techniques in a purely distributed memory MPSoC architecture that is composed of a frequency scaling module responsible for tuning the frequency of processors at run-time. Results show very promising in terms of adaptation capabilities for system with dynamic workload. Performance results demonstrate the effectiveness of the proposed approach when workload requirements for applications may vary, affecting the overall performance of the system. For validating the proposed approach we have implemented a multi-thread MJPEG decoder application and created an architecture model with/without perturbations in the system.
Index Terms:
MPSoC, homogeneous, PID, adaptive, NoC, distributed memory, RTOS
Citation:
Gabriel Marchesan Almeida, Sameer Varyani, Rémi Busseuil, Nicolas Hebert, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert, "Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism," reconfig, pp.382-387, 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
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