CSDL - Proceedings R

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-x

Message from the Chairs (PDF)

pp. xi

Organizing Committee (PDF)

pp. xii

Program Committee (PDF)

pp. xiii-xvi

Additional Reviewers (PDF)

pp. xvii

A Novel High-Density Single-Event Upset Hardened Configurable SRAM Applied to FPGA (Abstract)

pp. 1-5

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FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier (Abstract)

Malte Baesler

Thomas Teufel

pp. 6-11

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Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures (Abstract)

pp. 12-17

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MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs (Abstract)

pp. 18-23

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Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area (Abstract)

pp. 24-29

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A 10 Gbps OTN Framer Implementation Targeting FPGA Devices (Abstract)

pp. 30-35

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FPGA Implementations of BCD Multipliers (Abstract)

pp. 36-41

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Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations (Abstract)

pp. 42-47

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Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture (Abstract)

pp. 48-53

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PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems (Abstract)

pp. 54-58

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A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier (Abstract)

Carlos Minchola

Gustavo Sutter

pp. 59-64

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Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation (Abstract)

Marcus Jeitler

Jakob Lechner

pp. 65-70

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Runtime Memory Allocation in a Heterogeneous Reconfigurable Platform (Abstract)

Vlad-Mihai Sima

Koen Bertels

pp. 71-76

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A Systolic Array Based Architecture for Implementing Multivariate Polynomial Interpolation Tasks (Abstract)

Rafael A. Arce-Nazario

Edusmildo Orozco

Dorothy Bollman

pp. 77-82

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A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs (Abstract)

Alireza Rohani

Hamid R. Zarandi

pp. 83-88

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Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved Performance (Abstract)

Adwait Gupte

Phillip Jones

pp. 89-94

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Base-Calling in DNA Pyrosequencing with Reconfigurable Bayesian Network (Abstract)

Mingjie Lin

Yaling Ma

pp. 95-100

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FPGA-Based Online Induction Motor Multiple-Fault Detection with Fused FFT and Wavelet Analysis (Abstract)

E. Cabal-Yepez

R. A. Osornio-Rios

R. J. Romero-Troncoso

J. R. Razo-Hernandez

R. Lopez-Garcia

pp. 101-106

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A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA (Abstract)

pp. 107-112

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An FPGA-Based Custom High Performance Interconnection Network (Abstract)

pp. 113-118

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Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000 (Abstract)

pp. 119-124

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A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA (Abstract)

pp. 125-130

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Scalability Studies of the BLASTn Scan and Ungapped Extension Functions (Abstract)

Siddhartha Datta

Ron Sass

pp. 131-136

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Low Power RTL Exploration Mechanism Based on the Cache Parameters (Abstract)

pp. 137-142

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A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation (Abstract)

pp. 143-148

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Low Power, Reconfigurable Computing Platform for Spacecraft (Abstract)

pp. 149-154

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Hardware Accelerator for Full-Text Search (HAFTS) with Succinct Data Structure (Abstract)

pp. 155-160

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Triple Line-Based Playout for Go - An Accelerator for Monte Carlo Go (Abstract)

pp. 161-166

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Acceleration of Fractal Image Compression Using the Hardware-Software Co-design Methodology (Abstract)

Oscar Alvarado Nava

Arturo Díaz Pérez

pp. 167-171

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José Ignacio Benavides Benítez

FPGA Implementation of the Generalized Hough Transform (Abstract)

Sergio Rubén Geninatti

Manuel Hernández Calviño

Nicolás Guil Mata

Juan Gómez Luna

pp. 172-177

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An Optimized System for Multiple Sequence Alignment (Abstract)

Caglar Yilmaz

Mustafa Gök

pp. 178-182

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Protecting the NOEKEON Cipher against SCARE Attacks in FPGAs by Using Dynamic Implementations (Abstract)

pp. 183-188

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Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules (Abstract)

pp. 189-194

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Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and Peripherals (Abstract)

Marcio Juliato

Catherine Gebotys

pp. 195-200

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Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing (Abstract)

pp. 201-206

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Implementing a Protected Zone in a Reconfigurable Processor for Isolated Execution of Cryptographic Algorithms (Abstract)

pp. 207-212

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Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow (Abstract)

pp. 213-218

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Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation (Abstract)

pp. 219-224

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Lightweight Cryptography for FPGAs (Abstract)

Panasayya Yalla

Jens-Peter Kaps

pp. 225-230

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Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units (Abstract)

pp. 231-236

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Observing the Randomness in RO-Based TRNG (Abstract)

pp. 237-242

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DPL on Stratix II FPGA: What to Expect? (Abstract)

pp. 243-248

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FPGA Implementation of an Elliptic Curve Processor Using the GLV Method (Abstract)

Mark Hamilton

William P. Marnane

pp. 249-254

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Reconfigurable Hardware Implementation of Arithmetic Modulo Minimal Redundancy Cyclotomic Primes for ECC (Abstract)

pp. 255-260

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Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath (Abstract)

pp. 261-266

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A Framework for 2.5D NoC Exploration Using Homogeneous Networks over Heterogeneous Floorplans (Abstract)

Vitor de Paulo

Cristinel Ababei

pp. 267-272

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Overview of FPGA-Based Multiprocessor Systems (Abstract)

pp. 273-278

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Symmetric Multiprocessor Systems on FPGA (Abstract)

Jose Ignacio Martinez

pp. 279-283

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A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip (Abstract)

pp. 284-289

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Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips (Abstract)

pp. 290-295

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Self-Adaptive Network Interface (SANI): Local Component of a NoC Configuration Manager (Abstract)

R. Dafali

J-Ph. Diguet

pp. 296-301

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High-Level FPGA Programming through Mapping Process Networks to FPGA Resources (Abstract)

Fritz Mayer-Lindenberg

pp. 302-307

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Efficient PGA LFSR Implementation Whitens Pseudorandom Numbers (Abstract)

Leonard Colavito

Dennis Silage

pp. 308-313

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Composite Look-Up Table Gaussian Pseudo-Random Number Generator (Abstract)

Leonard Colavito

Dennis Silage

pp. 314-319

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Fernando Landeros Printzen

Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard (Abstract)

Héctor Borrayo-Sandoval

R. Parra-Michel

Luis F. González-Pérez

Claudia Feregrino-Uribe

pp. 320-325

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High Efficiency Space-Based Software Radio Architectures: A Minimum Size, Weight, and Power TeraOps Processor (Abstract)

pp. 326-331

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A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters (Abstract)

pp. 332-337

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Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications (Abstract)

pp. 338-343

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A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable Elements (Abstract)

Asadollah Shahbahrami

pp. 344-349

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Enhancing the Productivity of Radio Designers with RapidRadio (Abstract)

pp. 350-355

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Juan Fernando Eusse Giraldo

Signal Processing Domain Application Mapping on the Brick Reconfigurable Array (Abstract)

Ricardo Pezzuol Jacobi

pp. 356-361

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Multiprocessor Task Migration Implementation in a Reconfigurable Platform (Abstract)

pp. 362-367

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Virtualization of Computing Resources in RCS for Multi-task Stream Applications (Abstract)

pp. 368-373

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Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration Time (Abstract)

Abelardo Jara-Berrocal

Ann Gordon-Ross

pp. 374-379

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Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip (Abstract)

Muhammad Aqeel Wahlah

Kees Goossens

pp. 380-385

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New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA (Abstract)

pp. 386-391

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Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA (Abstract)

pp. 392-397

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Parallax-Docking and Reconfiguration of Field Programmable Robot Arrays Using an Intermittently-Powered One-Hot Controller (Abstract)

Mark G. Arnold

Jung H. Cho

pp. 398-403

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A Reconfigurable Architecture for Stereo-Assisted Detection of Point-Features for Robot Mapping (Abstract)

John Kalomiros

John Lygouras

pp. 404-409

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Walter de Britto Vidal Filho

Fuzzy Control for Cyclist Robot Stability Using FPGAs (Abstract)

Yesid E. Castro C.

Carlos H. Llanos

Leandro dos Santos Coelho

pp. 410-415

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FPGA Implementation for Direct Kinematics of a Spherical Robot Manipulator (Abstract)

pp. 416-421

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On the Implementation of Central Pattern Generators for Periodic Rhythmic Locomotion (Abstract)

Cesar Torres-Huitzil

pp. 422-426

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Bio-inspired Self-Testing and Self-Organizing Bit Slice Processors (Abstract)

André Stauffer

Joël Rossier

pp. 427-432

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Effects of Simplistic Online Synthesis for AMIDAR Processors (Abstract)

Stefan Döbrich

Christian Hochberger

pp. 433-438

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A Reconfigurable Design Framework for FPGA Adaptive Computing (Abstract)

pp. 439-444

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Implementation of a Dynamic Fault-Tolerance Scaling Technique on a Self-Adaptive Hardware Architecture (Abstract)

pp. 445-450

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FPGA Implementation of Izhikevich Spiking Neural Networks for Character Recognition (Abstract)

Kenneth L. Rice

Mohammad A. Bhuiyan

Tarek M. Taha

Christopher N. Vutsinas

Melissa C. Smith

pp. 451-456

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Author Index (PDF)

pp. 457-460

Publisher's Information (PDF)

pp. 462