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2009 International Conference on Reconfigurable Computing and FPGAs
Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA
Cancun, Quintana Roo, Mexico
December 09-December 11
ISBN: 978-0-7695-3917-1
| ASCII Text | x | ||
| Jochen Strunk, Toni Volkmer, Wolfgang Rehm, Heiko Schick, "Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA," Reconfigurable Computing and FPGAs, International Conference on, pp. 392-397, 2009 International Conference on Reconfigurable Computing and FPGAs, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/ReConFig.2009.24, author = {Jochen Strunk and Toni Volkmer and Wolfgang Rehm and Heiko Schick}, title = {Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA}, journal ={Reconfigurable Computing and FPGAs, International Conference on}, volume = {0}, year = {2009}, isbn = {978-0-7695-3917-1}, pages = {392-397}, doi = {http://doi.ieeecomputersociety.org/10.1109/ReConFig.2009.24}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Reconfigurable Computing and FPGAs, International Conference on TI - Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA SN - 978-0-7695-3917-1 SP392 EP397 A1 - Jochen Strunk, A1 - Toni Volkmer, A1 - Wolfgang Rehm, A1 - Heiko Schick, PY - 2009 KW - dynamic reconfiguration KW - run-time reconfiguration KW - FPGA KW - asynchronous FIFO KW - grid KW - NoC VL - 0 JA - Reconfigurable Computing and FPGAs, International Conference on ER - | |||
This paper examines the feasibility of utilizing a grid of asynchronously clocked run-time reconfigurable modules (RTRMs) on a dynamically and partially reconfigurable (DPR) FPGA. In contrast to a synchronously clocked grid studied in research, the design, the implementation, the performance and the resource utilization of an asynchronously clocked grid is shown. Such a run-time reconfigurable (RTR) grid on a FPGA can be utilized to dynamically offload compute functions on a host coupled system, providing multi-user and multi-context execution on behalf of user demands. For embedded systems it can be utilized as a highly dynamical platform by providing functional enhancement by module replacement during run-time. The presented platform leverages synthesis and development constraints and is able to increase the overall throughput by allowing multiple clock domains within the grid. The performance and the additional resource utilization of handling multiple clock domains is compared to synchronously clocked grids. As proof of concept a case study with a grid of 47 RTRMs is conducted on state of the art Virtex-5 FPGAs.
Index Terms:
dynamic reconfiguration, run-time reconfiguration, FPGA, asynchronous FIFO, grid, NoC
Citation:
Jochen Strunk, Toni Volkmer, Wolfgang Rehm, Heiko Schick, "Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA," reconfig, pp.392-397, 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
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