CSDL - Proceedings R

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-xi

Preface (PDF)

pp. xii

Organizing Committee (PDF)

pp. xiii

Program Committee (PDF)

pp. xiv-xv

Reviewers (PDF)

pp. xvi

Reconfigurable PDA for the Visually Impaired Using FPGAs (Abstract)

pp. 1-6

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Embedded Harmonic Control for Trajectory Planning in Large Environments (Abstract)

pp. 7-12

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José Hugo Barrón-Zambrano

Flexible Architecture for Three Classes of Optical Flow Extraction Algorithms (Abstract)

Cesar Torres-Huitzil

Mauricio Cerda

pp. 13-18

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Automatic Synthesis of Multiprocessor Systems from Parallel Programs under Preemptive Scheduling (Abstract)

pp. 19-24

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Design and Implementation of a Resource-Efficient Communication Architecture for Multiprocessors on FPGAs (Abstract)

Xiaofang Wang

Swetha Thota

pp. 25-30

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Automatic Instruction-Set Extensions with the Linear Complexity Spiral Search (Abstract)

Carlo Galuzzi

Dimitris Theodoropoulos

Roel Meeuws

Koen Bertels

pp. 31-36

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Lars Baunegaard With Jensen

A Real-Time Embedded System for Stereo Vision Preprocessing Using an FPGA (Abstract)

Anders Kjær-Nielsen

Anders Stengaard Sørensen

Norbert Krüger

pp. 37-42

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Finite Precision Analysis of the 3GPP Standard Turbo Decoder for Fixed-Point Implementation in FPGA Devices (Abstract)

Anabel Morales-Cortés

R. Parra-Michel

Luis F. González-Pérez

Gabriela Cervantes T.

pp. 43-48

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José Hugo Barrón-Zambrano

Parallel Processor for 3D Recovery from Optical Flow (Abstract)

Fernando Martin del Campo-Ramírez

Miguel Arias-Estrada

pp. 49-54

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A Reconfigurable Platform for Frequent Pattern Mining (Abstract)

pp. 55-60

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A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources (Abstract)

E. Huck

pp. 61-66

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Optimizing Partial Reconfiguration of Multi-context Architectures (Abstract)

pp. 67-72

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Automatic Construction of Large-Scale Regular Expression Matching Engines on FPGA (Abstract)

Yi-Hua E. Yang

Viktor K. Prasanna

pp. 73-78

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A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems (Abstract)

Juan Antonio Clemente

pp. 79-84

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Optimized Architectural Synthesis of Fixed-Point Datapaths (Abstract)

Octavio Nieto-Taladriz

pp. 85-90

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José Ignacio Benavides Benítez

Developing an MMX Extension for the MicroBlaze Soft Processor (Abstract)

Manuel Hernández Calvino

Sergio Rubén. Geninatti

pp. 91-96

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An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures (Abstract)

pp. 97-102

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Architectural Model and Resource Estimation for Distributed Hardware Implementation of Discrete Signal Transforms (Abstract)

Rafael A. Arce-Nazario

Manuel Jiménez

Domingo Rodríguez

pp. 103-108

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A Reconfiguration-Aware Floorplacer for FPGAs (Abstract)

pp. 109-114

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The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture (Abstract)

pp. 115-120

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Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs (Abstract)

pp. 121-126

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Integrating Logic Analyzer Functionality into VHDL Designs (Abstract)

pp. 127-132

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Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead (Abstract)

pp. 133-138

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Leveraging Firmware in Multichip Systems to Maximize FPGA Resources: An Application of Self-Partial Reconfiguration (Abstract)

pp. 139-144

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Finite Domain Constraints Based Delay Aware Placement Tool for FPOAs (Abstract)

Rohit Saraswat

Brandon Eames

pp. 145-150

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Arithmetic Operations and Their Energy Consumption in the Nios II Embedded Processor (Abstract)

pp. 151-156

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Operating System for Symmetric Multiprocessors on FPGA (Abstract)

Pablo Huerta

Javier Castillo

Carlos Sánchez

Jose Ignacio Martínez

pp. 157-162

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Dynamically Reconfigurable Split Cache Architecture (Abstract)

Luiza M.N. Coutinho

Jose L.D. Mendes

Carlos A.P.S. Martins

pp. 163-168

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Configurable-System-on-Programmable-Chip for Power Electronics Control Applications (Abstract)

pp. 169-174

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Parallel Backprojector for Cone-Beam Computer Tomography (Abstract)

Nikolay Sorokin

pp. 175-180

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Key Research Issues for Reconfigurable Network-on-Chip (Abstract)

pp. 181-186

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SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips (Abstract)

pp. 187-192

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Design Space Exploration and Performance Analysis for the Modular Design of CVS in a Heterogeneous MPSoC (Abstract)

pp. 193-198

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Part-E - A Tool for Reconfigurable System Design (Abstract)

pp. 199-204

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VIS2SOUND on Reconfigurable Hardware (Abstract)

pp. 205-210

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A Fast Emulation-Based NoC Prototyping Framework (Abstract)

pp. 211-216

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Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices (Abstract)

Sohan Purohit

Sai Rahul Chalamalasetti

Martin Margala

Pasquale Corsonello

pp. 217-222

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Reconfigurability-Aware Structural Mapping for LUT-Based FPGAs (Abstract)

Karel Bruneel

Dirk Stroobandt

pp. 223-228

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Fast Implementation of a Bio-inspired Model for Decentralized Gathering (Abstract)

Bernard Girau

Cesar Torres-Huitzel

pp. 229-234

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Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoC (Abstract)

pp. 235-240

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Lars Baunegaard With Jensen

A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors (Abstract)

pp. 241-246

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Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable Processor (Abstract)

pp. 247-252

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Dynamic Self-Rescheduling of Tasks over a Heterogeneous Platform (Abstract)

pp. 253-258

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Sequence Alignment with Traceback on Reconfigurable Hardware (Abstract)

Scott Lloyd

Quinn O. Snell

pp. 259-264

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A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI (Abstract)

pp. 265-270

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FPGA Implementation of Pseudo Random Number Generators for Monte Carlo Methods in Quantitative Finance (Abstract)

pp. 271-276

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Jesus M. Alvarez-Llorente

A Pthreads-Based MPI-1 Implementation for MMU-Less Machines (Abstract)

Juan A. Rico-Gallego

Francisco J. Perogil-Duque

Pedro P. Antúnez-Gómez

Juan C. D

pp. 277-282

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A Hardware Filesystem Implementation for High-Speed Secondary Storage (Abstract)

Ashwin A. Mendon

Ron Sass

pp. 283-288

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Rene de J. Romero-Troncoso

A Real-Time FPGA Based Platform for Applications in Mechatronics (Abstract)

Roque A. Osornio-Rios

Luis Morales-Velazquez

J. Jesus de Santiago-Perez

Rooney de J. Rivera-Guillen

J. de Jesus Rangel-Magdaleno

pp. 289-294

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Disparity Map Hardware Accelerator (Abstract)

pp. 295-300

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A Novel Rekeying Message Authentication Procedure Based on Winternitz OTS and Reconfigurable Hardware Architectures (Abstract)

pp. 301-306

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Paulo S. Brandao do Nascimento

A Temporal Partitioning Methodology for Reconfigurable High Performance Computers (Abstract)

Victor W.C. de Medeiros

Viviane L.S. Souza

Abner C. Barros

Manoel Eusebio de Lima

pp. 307-312

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Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs (Abstract)

pp. 313-318

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Friedrich Mayer-Lindenberg

Reconfigurable Cell Architecture for Systolic and Pipelined Computing Datapaths (Abstract)

Abdulrahman Hanoun

Bassel Soudan

pp. 319-324

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Implementations and Optimizations of Pipeline FFTs on Xilinx FPGAs (Abstract)

Bin Zhou

David Hwang

pp. 325-330

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Generalised Parallel Bilinear Interpolation Architecture for Vision Systems (Abstract)

Suhaib A. Fahmy

pp. 331-336

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An FFT/IFFT Design versus Altera and Xilinx Cores (Abstract)

C. Gonzalez-Concejero

pp. 337-342

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Using a CSP Based Programming Model for Reconfigurable Processor Arrays (Abstract)

Zain-ul-Abdin

Bertil Svensson

pp. 343-348

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A Novel FPGA Implementation of a Wideband Sonar System for Target Motion Estimation (Abstract)

pp. 349-354

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Fernando Martín del Campo

Hybrid Architecture for Data-Dependent Superimposed Training in Digital Receivers (Abstract)

René Cumplido

Roberto Perez-Andrade

A.G. Orozco-Lugo

pp. 355-360

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A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components (Abstract)

pp. 361-366

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Jose Juan Garcia-Hernandez

FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems (Abstract)

Claudia Feregrino-Uribe

Rene Cumplido

pp. 367-372

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Universal Wavelet Kernel Implementation Using Reconfigurable Hardware (Abstract)

Christophe Desmouliers

Erdal Oruklu

Jafar Saniie

pp. 373-378

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Design and Implementation of a Multi-standard Interleaver for 802.11a, 802.11n, 802.16e & DVB Standards (Abstract)

Carlos R. Sánchez-Ortiz

R. Parra-Michel

M.E. Guzmán-Rentería

pp. 379-384

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Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings (Abstract)

Knut Wold

Chik How Tan

pp. 385-390

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Parametric, Secure and Compact Implementation of RSA on FPGA (Abstract)

Ersin Öksüzoglu

Erkay Savas

pp. 391-396

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FPGA Implementation of an Elliptic Curve Cryptosystem over GF(3^m) (Abstract)

Ilker Yavuz

Siddika Berna Örs Yalçin

Çetin Kaya Koç

pp. 397-402

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Enhanced Correlation Power Analysis Using Key Screening Technique (Abstract)

pp. 403-408

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Enhancing an Embedded Processor Core with a Cryptographic Unit for Speed and Security (Abstract)

pp. 409-414

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Triple Rail Logic Robustness against DPA (Abstract)

pp. 415-420

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FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks (Abstract)

Ignacio Algredo-Badillo

Claudia Feregrino-Uribe

René Cumplido

Miguel Morales-Sandoval

pp. 421-426

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High Performance Implementation of a Public Key Block Cipher - MQQ, for FPGA Platforms (Abstract)

pp. 427-432

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Power Consumption Estimations vs Measurements for FPGA-Based Security Cores (Abstract)

Dimitrios Meintanis

Ioannis Papaefstathiou

pp. 433-437

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Celator: A Multi-algorithm Cryptographic Co-processor (Abstract)

pp. 438-443

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Z. Jezabel Guzmán Zavaleta

A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation (Abstract)

Claudia Feregrino Uribe

René Cumplido

pp. 444-449

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Forward-Secure Content Distribution to Reconfigurable Hardware (Abstract)

pp. 450-455

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Author Index (PDF)

pp. 456-459

Publisher's Information (PDF)

pp. 460