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2008 International Conference on Reconfigurable Computing and FPGAs
A Temporal Partitioning Methodology for Reconfigurable High Performance Computers
December 03-December 05
ISBN: 978-0-7695-3474-9
| ASCII Text | x | ||
| Paulo S. Brandao do Nascimento, Victor W.C. de Medeiros, Viviane L.S. Souza, Abner C. Barros, Manoel Eusebio de Lima, "A Temporal Partitioning Methodology for Reconfigurable High Performance Computers," Reconfigurable Computing and FPGAs, International Conference on, pp. 307-312, 2008 International Conference on Reconfigurable Computing and FPGAs, 2008. | |||
| BibTex | x | ||
| @article{ 10.1109/ReConFig.2008.73, author = {Paulo S. Brandao do Nascimento and Victor W.C. de Medeiros and Viviane L.S. Souza and Abner C. Barros and Manoel Eusebio de Lima}, title = {A Temporal Partitioning Methodology for Reconfigurable High Performance Computers}, journal ={Reconfigurable Computing and FPGAs, International Conference on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3474-9}, pages = {307-312}, doi = {http://doi.ieeecomputersociety.org/10.1109/ReConFig.2008.73}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Reconfigurable Computing and FPGAs, International Conference on TI - A Temporal Partitioning Methodology for Reconfigurable High Performance Computers SN - 978-0-7695-3474-9 SP307 EP312 A1 - Paulo S. Brandao do Nascimento, A1 - Victor W.C. de Medeiros, A1 - Viviane L.S. Souza, A1 - Abner C. Barros, A1 - Manoel Eusebio de Lima, PY - 2008 KW - Temporal Partitioning KW - Reconfigurable Computers KW - FPGAs VL - 0 JA - Reconfigurable Computing and FPGAs, International Conference on ER - | |||
This paper presents a Design Space Exploration(DSE) methodology based on a temporal partitioning strategy for mapping of massive computational dataflow problems into FPGAs. In this approach the FPGAs work as co-processors in a hypothetic reconfigurable computing architecture. The temporal partitioning is based on Tabu Search strategies and libraries of IP-cores. This methodology allows Design Space Exploration for optimization of dataflow implementation into the FPGA and pre-runtime analysis. Results of this DSE technique, for synthetic benchmarks, have reached very good performance and sometimes better than others in the literature.
Index Terms:
Temporal Partitioning, Reconfigurable Computers, FPGAs
Citation:
Paulo S. Brandao do Nascimento, Victor W.C. de Medeiros, Viviane L.S. Souza, Abner C. Barros, Manoel Eusebio de Lima, "A Temporal Partitioning Methodology for Reconfigurable High Performance Computers," reconfig, pp.307-312, 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
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