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2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)
Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture
San Luis Potosi
September 20-September 22
ISBN: 1-4244-0689-7
| ASCII Text | x | ||
| F. Dittmann, A. Rettberg, R. Weber, "Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture," Reconfigurable Computing and FPGAs, International Conference on, pp. 1-8, 2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006), 2006. | |||
| BibTex | x | ||
| @article{ 10.1109/RECONF.2006.307778, author = {F. Dittmann and A. Rettberg and R. Weber}, title = {Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture}, journal ={Reconfigurable Computing and FPGAs, International Conference on}, volume = {0}, year = {2006}, isbn = {1-4244-0689-7}, pages = {1-8}, doi = {http://doi.ieeecomputersociety.org/10.1109/RECONF.2006.307778}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Reconfigurable Computing and FPGAs, International Conference on TI - Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture SN - 1-4244-0689-7 SP1 EP8 A1 - F. Dittmann, A1 - A. Rettberg, A1 - R. Weber, PY - 2006 KW - FDCT-IDCT algorithm KW - reconfigurable bit-serial synchronous architecture KW - path concept KW - patented synchronous bit-serial pipelined architecture KW - systematic bit-serial processing VL - 0 JA - Reconfigurable Computing and FPGAs, International Conference on ER - | |||
This paper develops path concepts for the execution of different algorithms on a reconfigurable architecture. New architecture concepts demand for permanent evaluation of such extensions, also including validating case studies. The recently patented synchronous bit-serial pipelined architecture, which we investigate in this paper, comprises synchronous and systematic bit-serial processing without a central controlling instance. It targets future high speed applications due to the abdication of long wires. The application specificity of the basic version of the architecture can be overcome by so called routers, achieving a reconfigurable system. This paper focuses on the difficulty to conceptualize these routers and proposes several variations for implementation. The case study, which comprises a combined version of the FDCT/IDCT algorithm, serves as an application example for the reconfigurability of the architecture
Index Terms:
FDCT-IDCT algorithm, reconfigurable bit-serial synchronous architecture, path concept, patented synchronous bit-serial pipelined architecture, systematic bit-serial processing
Citation:
F. Dittmann, A. Rettberg, R. Weber, "Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture," reconfig, pp.1-8, 2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006), 2006
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