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Eighth Pacific Rim International Symposium on Dependable Computing (PRDC'01)
Validating Real-Time Constraints in Embedded Systems
Seoul, Korea
December 17-December 19
ISBN: 0-7695-1414-6
| ASCII Text | x | ||
| R.K. Shyamasundar, J.V. Aghav, "Validating Real-Time Constraints in Embedded Systems," Pacific Rim International Symposium on Dependable Computing, IEEE, pp. 347, Eighth Pacific Rim International Symposium on Dependable Computing (PRDC'01), 2001. | |||
| BibTex | x | ||
| @article{ 10.1109/PRDC.2001.992719, author = {R.K. Shyamasundar and J.V. Aghav}, title = {Validating Real-Time Constraints in Embedded Systems}, journal ={Pacific Rim International Symposium on Dependable Computing, IEEE}, volume = {0}, year = {2001}, isbn = {0-7695-1414-6}, pages = {347}, doi = {http://doi.ieeecomputersociety.org/10.1109/PRDC.2001.992719}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Pacific Rim International Symposium on Dependable Computing, IEEE TI - Validating Real-Time Constraints in Embedded Systems SN - 0-7695-1414-6 SP EP A1 - R.K. Shyamasundar, A1 - J.V. Aghav, PY - 2001 KW - Embedded Systems KW - Esterel KW - RealTime Systems KW - Synchronous Languages KW - Validation & Verification. VL - 0 JA - Pacific Rim International Symposium on Dependable Computing, IEEE ER - | |||
There is a growing demand for software tools that can assist in designing, analyzing and validating embedded real-time system applications. ESTEREL a synchronous language, is widely used in the development of embedded systems and hardware/software codesign. In this paper, we describe a method that uses timed annotations for ESTEREL programs that makes it possible to predict the Timing constraints required to be satisfied by the embedded system. Using the specified annotations and the programming environment of ESTEREL we describe a method and a tool for validating the concrete realization relative to time-annotated ESTEREL specifications. Also, the method derives time constraints to be satisfied by the concrete architectures for realizing the logical specification. We shall illustrate the technique with examples as well as the structure of the tool implemented.
Index Terms:
Embedded Systems, Esterel, RealTime Systems, Synchronous Languages, Validation & Verification.
Citation:
R.K. Shyamasundar, J.V. Aghav, "Validating Real-Time Constraints in Embedded Systems," prdc, pp.347, Eighth Pacific Rim International Symposium on Dependable Computing (PRDC'01), 2001
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