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2010 18th Euromicro Conference on Parallel, Distributed and Network-based Processing
Lessons Learnt Porting Parallelisation Techniques for Irregular Codes to NUMA Systems
Pisa, Italy
February 17-February 19
ISBN: 978-0-7695-3939-3
This work presents a study undertaken to characterise the behaviour of some parallelisation techniques for irregular codes, previously developed for SMP architectures, on a several-node SMP NUMA system. The main objective is to determine the performance effect of bus contention and cache coherency in such a complex architecture. Results show that: (1) cores which share a socket can be considered as independent processors in this context; (2) for big data sizes, the effect of sharing a bus degrades the performance but masks the cache coherency effects and (3) the NUMA-ratio is a critical factor on irregular codes. These results allow us to study the effect in performance of the thread-to-core mappings and memory allocation policies.
Index Terms:
Irregular Codes, Itanium2, Hardware Counters
Citation:
Juan Ángel Lorenzo, Juan Carlos Pichel, David LaFrance-Linden, Francisco Fernández Rivera, David Expósito Singh, "Lessons Learnt Porting Parallelisation Techniques for Irregular Codes to NUMA Systems," pdp, pp.213-217, 2010 18th Euromicro Conference on Parallel, Distributed and Network-based Processing, 2010
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