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Eleventh Euromicro Conference on Parallel, Distributed and Network-Based Processing
An Accelerator for Double Precision Floating Point Operations
Genova, Italy
February 05-February 07
ISBN: 0-7695-1875-3
| ASCII Text | x | ||
| G. Danese, I. De Lotto, F. Leporati, M. Scaricabarozzi, A. Spelgatti, "An Accelerator for Double Precision Floating Point Operations," 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008), pp. 57, Eleventh Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2003. | |||
| BibTex | x | ||
| @article{ 10.1109/EMPDP.2003.1183566, author = {G. Danese and I. De Lotto and F. Leporati and M. Scaricabarozzi and A. Spelgatti}, title = {An Accelerator for Double Precision Floating Point Operations}, journal ={16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008)}, volume = {0}, year = {2003}, issn = {1066-6192}, pages = {57}, doi = {http://doi.ieeecomputersociety.org/10.1109/EMPDP.2003.1183566}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008) TI - An Accelerator for Double Precision Floating Point Operations SN - 1066-6192 SP EP A1 - G. Danese, A1 - I. De Lotto, A1 - F. Leporati, A1 - M. Scaricabarozzi, A1 - A. Spelgatti, PY - 2003 KW - null VL - 0 JA - 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008) ER - | |||
We describe DPFPA (Double Precision Floating Point Accelerator) an FPGA based coprocessor interfaced to the CPU through he PCI bus; it is conceived to accelerate the evaluation of double precision floating point operations. This coprocessor is based on two double precision floating point units: a pipelined adder and a pipelined multiplier. The work is part of a global project aimed to design and build a parallel system made up by a cluster of accelerated works ations. First estimations of performance have been obtained, using a similar board developed at Fermilab (Batavia, IL) with less recent components and working at half the frequency with respect to DPFPA. Even in his case, a substantial acceleration with respect to the execution on Intel?s CPU based mother-board was observed.
Citation:
G. Danese, I. De Lotto, F. Leporati, M. Scaricabarozzi, A. Spelgatti, "An Accelerator for Double Precision Floating Point Operations," pdp, pp.57, Eleventh Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2003
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