- P
- PAS
- 1997
- 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis (pAs '97)
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2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis (pAs '97) Aizu-Wakamatsu, Fukushima, JAPAN March 17-March 21 ISBN: 0-8186-7870-4 Table of Contents
 | Invited Lectures |
R. Gray, Dept. of Comput. Sci., Dartmouth Coll., Hanover, NH, USA
D. Kotz, Dept. of Comput. Sci., Dartmouth Coll., Hanover, NH, USA
S. Nog, Dept. of Comput. Sci., Dartmouth Coll., Hanover, NH, USA
D. Rus, Dept. of Comput. Sci., Dartmouth Coll., Hanover, NH, USA
G. Cybenko, Dept. of Comput. Sci., Dartmouth Coll., Hanover, NH, USA pp. 8
M. Sato, Electrotech. Lab., Ibaraki, Japan pp. 25
 | Memory Performance and Architecture |
T. Ikedo, Computer Architecture Lab. The University of Aizu pp. 50
K.W. Rudd, Comput. Syst. Lab., Stanford Univ., CA, USA
M.J. Flynn, Comput. Syst. Lab., Stanford Univ., CA, USA pp. 74
 | Communication Networks and Routing |
Hyunseung Choo, Dept. of Comput. Sci. & Eng., Texas Univ., Arlington, TX, USA
Hee Yong Youn, Dept. of Comput. Sci. & Eng., Texas Univ., Arlington, TX, USA
Seong-Moo Yoo, Dept. of Comput. Sci. & Eng., Texas Univ., Arlington, TX, USA pp. 83
Seong-Moo Yoo, Columbus State University and The University of Texas at Arlington
Hee Yong Youn, Columbus State University and The University of Texas at Arlington pp. 97
Chih-Ming Lai, Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Jyh-Jong Tsay, Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan pp. 104
Jean-Luc Gaudiot, University of Southern California, Los Angeles, California, USA
Tom DeBoni, Lawrence Livermore National Laboratory, Livermore, California, USA
John Feo, Lawrence Livermore National Laboratory, Livermore, California, USA
Wim Böhm, Colorado State University, Fort Collins, Colorado, USA
Walid Najjar, Colorado State University, Fort Collins, Colorado, USA pp. 112
R.D. Dietz, Parallel Processing Laboratory The University of Iowa
T.L. Casavant, Parallel Processing Laboratory The University of Iowa
T.E. Scheetz, Parallel Processing Laboratory The University of Iowa
T.A. Braun, Parallel Processing Laboratory The University of Iowa pp. 124
 | Allocation and Load Balancing |
Thomas Sterling, California Institute of Technology NASA/Jet Propulsion Laboratory pp. 143
Kun-Ming Yu, Dept. of Comput. Sci., Chung-Hua Polytech. Inst., Hsin-Chu, Taiwan
S.J.-W. Wu, Dept. of Comput. Sci., Chung-Hua Polytech. Inst., Hsin-Chu, Taiwan
Tzung-Pei Hong, Dept. of Comput. Sci., Chung-Hua Polytech. Inst., Hsin-Chu, Taiwan pp. 159
Gil-Haeng Lee, ATM TMN Sect., Electron. & Telecommun. Res. Inst., Taejon, South Korea pp. 166
 | Algorithms and Techniques |
 | Synchronization, Communication, and Prefetching |
Chan, National University of Singapore
Wai-wai, National University of Singapore
Chi, National University of Singapore
Chi-hung, National University of Singapore pp. 225
 | Tools, Environment, and Techniques |
Ted Lewis, Naval Postgraduate School, Code CS, Monterey, CA USA pp. 248
 | Simulation, Tools, and Techniques |
Yasuhiro Oue, Massively Parallel Systems Sanyo Laboratory, RWCP pp. 316
 | Parallel Systems and Algorithms |
D.B. Barsky, Dept. of Electron. & Electr. Eng., Surrey Univ., Guildford, UK
A.V. Shafarenko, Dept. of Electron. & Electr. Eng., Surrey Univ., Guildford, UK pp. 356
Jun Ma, Dept. of Comput. Sci., Shandong Univ., Jinan, China
K. Iwama, Dept. of Comput. Sci., Shandong Univ., Jinan, China
Qian-Ping Gu, Dept. of Comput. Sci., Shandong Univ., Jinan, China pp. 384 Usage of this product signifies your acceptance of the Terms of Use.
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