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| Sebastian Siegel, Rainer Schaffer, Renate Merker, "Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels," Parallel Computing in Electrical Engineering, 2004. International Conference on, pp. 173-180, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06), 2006. | |||
| BibTex | x | ||
| @article{ 10.1109/PARELEC.2006.33, author = {Sebastian Siegel and Rainer Schaffer and Renate Merker}, title = {Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels}, journal ={Parallel Computing in Electrical Engineering, 2004. International Conference on}, volume = {0}, year = {2006}, isbn = {0-7695-2554-7}, pages = {173-180}, doi = {http://doi.ieeecomputersociety.org/10.1109/PARELEC.2006.33}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Parallel Computing in Electrical Engineering, 2004. International Conference on TI - Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels SN - 0-7695-2554-7 SP173 EP180 A1 - Sebastian Siegel, A1 - Rainer Schaffer, A1 - Renate Merker, PY - 2006 KW - null VL - 0 JA - Parallel Computing in Electrical Engineering, 2004. International Conference on ER - | |||
We exploit the parallelismon both levels of our processor array by a parameterized two-level partitioning of the algorithm. To obtain a significant speed-up such partitioning parameters are selected which match the target architecture and require a minimum number of additional instructions for SWP.
Through this partitioning communication within the processor array appears to be necessary on a large scale. By a detailed examination, which is automatically performed by integer linear programming, we extract and eliminate redundant communication. Hence, our realization of the edge detection algorithm is efficient in terms of energy consumption caused by communication within the processor array. And we obtain a significant speed-up by exploiting both levels of parallelism.