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International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04)
Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment
Dresden, Germany
September 07-September 10
ISBN: 0-7695-2080-4
| ASCII Text | x | ||
| J. Schneider, V. Kotzsch, St. R?, "Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment," Parallel Computing in Electrical Engineering, 2004. International Conference on, pp. 177-180, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004. | |||
| BibTex | x | ||
| @article{ 10.1109/PCEE.2004.24, author = {J. Schneider and V. Kotzsch and St. R?}, title = {Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment}, journal ={Parallel Computing in Electrical Engineering, 2004. International Conference on}, volume = {0}, year = {2004}, isbn = {0-7695-2080-4}, pages = {177-180}, doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.24}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Parallel Computing in Electrical Engineering, 2004. International Conference on TI - Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment SN - 0-7695-2080-4 SP177 EP180 A1 - J. Schneider, A1 - V. Kotzsch, A1 - St. R?, PY - 2004 KW - null VL - 0 JA - Parallel Computing in Electrical Engineering, 2004. International Conference on ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.24
With this demonstrator we present a new reuse based design methodology for the development of FEC (Forward Error Correction) applications for reconfigurable SoC (System-on-Chip) architectures. This approach enables the reuse of well tested and optimized RS- (Reed-Solomon) codec modules consisting of both HW and SW. Specific RS codec modules can be generated by generator tools. In order to automate the reuse process for dynamically reconfigurable SoCs, the generator tool supports the generation of design modules, interfaces and design flows. We examined our design methodology and RS codec modules within the SFB-358 demonstrator.
Citation:
J. Schneider, V. Kotzsch, St. R?, "Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment," parelec, pp.177-180, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004
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