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2011 International Conference on Parallel Architectures and Compilation Techniques
Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour
Galveston, Texas USA
October 10-October 14
ISBN: 978-0-7695-4566-0
ASCII Text
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Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato, "Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour," Parallel Architectures and Compilation Techniques, International Conference on, pp. 214, 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011.
 
 
BibTex
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@article{ 10.1109/PACT.2011.47,
author = {Alejandro Valero and Julio Sahuquillo and Salvador Petit and Pedro López and José Duato},
title = {Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour},
journal ={Parallel Architectures and Compilation Techniques, International Conference on},
volume = {0},
year = {2011},
issn = {1089-795X},
pages = {214},
doi = {http://doi.ieeecomputersociety.org/10.1109/PACT.2011.47},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Parallel Architectures and Compilation Techniques, International Conference on
TI - Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour
SN - 1089-795X
SP
EP
A1 - Alejandro Valero,
A1 - Julio Sahuquillo,
A1 - Salvador Petit,
A1 - Pedro López,
A1 - José Duato,
PY - 2011
KW - Last-Level Cache
KW - MRU-Tour
KW - replacement algorithm
VL - 0
JA - Parallel Architectures and Compilation Techniques, International Conference on
ER -
 
Last-Level Caches (LLCs) implement the LRU algorithm to exploit temporal locality, but its performance is quite far of Belady's optimal algorithm as the number of ways increases. One of the main reasons because of LRU does not reach good performance in LLCs is that this policy forces a block to descend until the bottom of the stack before eviction. Nevertheless, most of the blocks that leave the MRU position are not referenced again before eviction. This work pursues to select candidate blocks to be victimized before reaching the bottom of the stack. To this end, this work defines the number of MRU-Tours (MRUTs) of a block as the number of times that a block enters in the MRU position during its live time. Based on the fact that most of the blocks exhibit a single MRUT, this work presents the family of MRUT-based algorithms aimed at exploiting this block behavior to improve performance.
Index Terms:
Last-Level Cache, MRU-Tour, replacement algorithm
Citation:
Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato, "Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour," pact, pp.214, 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
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