Searching...
Advanced Search
P
PACT
2009
2009 18th International Conference on Parallel Architectures and Compilation Techniques
This Publication
Digital Library
Advanced Search
This Publication
Subscribe to this Publication
Login to access your subscribed content
Bibliographic References
ASCII Text
BibTex
Refworks Procite/RefMan
2009 18th International Conference on Parallel Architectures and Compilation Techniques
Raleigh, North Carolina, USA
September 12-September 16
ISBN: 978-0-7695-3771-9
Table of Contents
Papers
Cover Art
(PDF)
pp. C4,C1
ABSTRACT
PDF
Title Page i
(PDF)
pp. i
ABSTRACT
PDF
Title Page iii
(PDF)
pp. iii
ABSTRACT
PDF
Copyright Page
(PDF)
pp. iv
ABSTRACT
PDF
Table of Contents
(PDF)
pp. v-vii
ABSTRACT
PDF
Message from General Chairs
(PDF)
pp. viii
ABSTRACT
PDF
Message from Program Chairs
(PDF)
pp. ix
ABSTRACT
PDF
Organizing Committee
(PDF)
pp. x
ABSTRACT
PDF
Program Committee
(PDF)
pp. xi-xii
ABSTRACT
PDF
Additional Reviewers
(PDF)
pp. xiii-xiv
ABSTRACT
PDF
Keynote: Why are Graphics Systems so Fast?
(PDF)
pp. xv
ABSTRACT
PDF
Keynote: Pushing the Limits: Scientific Computing on Extreme Platforms
(PDF)
pp. xvi
ABSTRACT
PDF
Adaptive Locks: Combining Transactions and Locks for Efficient Concurrency
(Abstract)
Takayuki Usui
Reimer Behrends
Jacob Evans
Yannis Smaragdakis
pp. 3-14
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading
(Abstract)
Carlos Madriles
Pedro López
Josep Maria Codina
Enric Gibert
Fernando Latorre
Alejandro Martínez
Raul Martínez
Antonio González
pp. 15-25
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
(Abstract)
Abhishek Bhattacharjee
Margaret Martonosi
pp. 29-40
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs
(Abstract)
Rajkishore Barik
Vivek Sarkar
pp. 41-52
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Quantifying the Potential of Program Analysis Peripherals
(Abstract)
Mohit Tiwari
Shashidhar Mysore
Timothy Sherwood
pp. 53-63
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor
(Abstract)
Tarik Saidani
Joel Falcou
Claude Tadonki
Lionel Lacassagne
Daniel Etiemble
pp. 67-76
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
A Task-Centric Memory Model for Scalable Accelerator Architectures
(Abstract)
John H. Kelm
Daniel R. Johnson
Steven S. Lumetta
Matthew I. Frank
Sanjay J. Patel
pp. 77-87
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
SHIP: Scalable Hierarchical Power Control for Large-Scale Data Centers
(Abstract)
Xiaorui Wang
Ming Chen
Charles Lefurgy
Tom W. Keller
pp. 91-100
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Exploring Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and Durable Memory Architectures
(Abstract)
Wangyuan Zhang
Tao Li
pp. 101-112
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Core-Selectability in Chip Multiprocessors
(Abstract)
Hashem Hashemi Najaf-abadi
Niket Kumar Choudhary
Eric Rotenberg
pp. 113-122
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Chainsaw: Using Binary Matching for Relative Instruction Mix Comparison
(Abstract)
Tipp Moseley
Dirk Grunwald
Ramesh Peri
pp. 125-135
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
tm_db: A Generic Debugging Library for Transactional Programs
(Abstract)
Maurice Herlihy
Yossi Lev
pp. 136-145
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
StealthTest: Low Overhead Online Software Testing Using Transactional Memory
(Abstract)
Jayaram Bobba
Weiwei Xiong
Luke Yen
Mark D. Hill
David A. Wood
pp. 146-155
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
CPROB: Checkpoint Processing with Opportunistic Minimal Recovery
(Abstract)
Andrew Hilton
Neeraj Eswaran
Amir Roth
pp. 159-168
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Architecture Support for Improving Bulk Memory Copying and Initialization Performance
(Abstract)
Xiaowei Jiang
Yan Solihin
Li Zhao
Ravishankar Iyer
pp. 169-180
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Oblivious Routing in On-Chip Bandwidth-Adaptive Networks
(Abstract)
Myong Hyon Cho
Mieszko Lis
Keun Sup Shim
Michel Kinsy
Tina Wen
Srinivas Devadas
pp. 181-190
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Exploiting Parallelism with Dependence-Aware Scheduling
(Abstract)
Xiaotong Zhuang
Alexandre E. Eichenberger
Yangchun Luo
Kevin O'Brien
Kathryn O'Brien
pp. 193-202
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs
(Abstract)
Carlos Luque
Miquel Moreto
Francisco J. Cazorla
Roberto Gioiosa
Alper Buyuktosunoglu
Mateo Valero
pp. 203-213
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures
(Abstract)
Amir H. Hormati
Yoonseo Choi
Manjunath Kudlur
Rodric Rabbah
Trevor Mudge
Scott Mahlke
pp. 214-223
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
DDCache: Decoupled and Delegable Cache Data and Metadata
(Abstract)
Hemayet Hossain
Sandhya Dwarkadas
Michael C. Huang
pp. 227-236
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Zero-Value Caches: Cancelling Loads that Return Zero
(Abstract)
Mafijul Md. Islam
Per Stenstrom
pp. 237-245
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
(Abstract)
Qingda Lu
Jiang Lin
Xiaoning Ding
Zhao Zhang
Xiaodong Zhang
P. Sadayappan
pp. 246-257
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System
(Abstract)
Daniel Molka
Daniel Hackenberg
Robert Schöne
Matthias S. Müller
pp. 261-270
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling
(Abstract)
Basilio B. Fraguela
Yevgen Voronenko
Markus Püschel
pp. 271-280
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Analytical Modeling of Pipeline Parallelism
(Abstract)
Angeles Navarro
Rafael Asenjo
Siham Tabik
Calin Cascaval
pp. 281-290
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
(Abstract)
Marc Lupon
Grigorios Magklis
Antonio González
pp. 293-302
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Improving Signatures by Locality Exploitation for Transactional Memory
(Abstract)
Ricardo Quislant
Eladio Gutierrez
Oscar Plata
Emilio L. Zapata
pp. 303-312
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading
(Abstract)
Leo Porter
Bumyong Choi
Dean M. Tullsen
pp. 313-324
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Polyhedral-Model Guided Loop-Nest Auto-Vectorization
(Abstract)
Konrad Trifunovic
Dorit Nuzman
Albert Cohen
Ayal Zaks
Ira Rosen
pp. 327-337
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Region Based Structure Layout Optimization by Selective Data Copying
(Abstract)
Sandya S. Mannarswamy
Ramaswamy Govindarajan
Rishi Surendran
pp. 338-347
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors
(Abstract)
Qingda Lu
Christophe Alias
Uday Bondhugula
Thomas Henretty
Sriram Krishnamoorthy
J. Ramanujam
Atanas Rountev
P. Sadayappan
Yongjian Chen
Haibo Lin
Tin-fook Ngai
pp. 348-357
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors
(Abstract)
Lei Jin
Sangyeun Cho
pp. 361-371
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Using Aggressor Thread Information to Improve Shared Cache Management for CMPs
(Abstract)
Wanli Liu
Donald Yeung
pp. 372-383
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Cache Sharing Management for Performance Fairness in Chip Multiprocessors
(Abstract)
Xing Zhou
Wenguang Chen
Weimin Zheng
pp. 384-393
ABSTRACT
PDF
PURCHASE ARTICLE: $19
IEEE
Xplore
Subscribers
Author Index
(PDF)
pp. 394-395
ABSTRACT
PDF
Publisher's Information
(PDF)
pp. 396
ABSTRACT
PDF
Peer Review Notice
|
Give Us Feedback
Usage of this product signifies your acceptance of the
Terms of Use
.
Open
Download
