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- PACT
- 2007
- 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)
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16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007) Brasov, Romania September 15-September 19 ISBN: 0-7695-2944-5 Table of Contents
 | Introduction |
 | Hardware Track (Session 1): Systems |
Miquel Pericas, Universitat Politecnica de Catalunya, Spain; Barcelona Supercomputing Center, Spain
Mateo Valero, Universitat Politecnica de Catalunya, Spain; Barcelona Supercomputing Center, Spain pp. 13-24
 | Software Track (Session 2): Pipelining |
 | Hardware Track (Session 3): Verification & Security |
 | Software Track (Session 4): Optimizations |
 | Hardware Track (Session 5): Saving Energy |
Feihui Li, Pennsylvania State University, USA pp. 163-174
Bo Zhai, University of Michigan-Ann Arbor, USA pp. 175-188
 | Software Track (Session 6): Algorithms |
Xuejun Yang, National University of Defense Technology, China
Yunfei Du, National University of Defense Technology, China
Panfeng Wang, National University of Defense Technology, China
Hongyi Fu, National University of Defense Technology, China
Jia Jia, National University of Defense Technology, China
Zhiyuan Wang, National University of Defense Technology, China
Guang Suo, National University of Defense Technology, China pp. 199-212
 | Hardware Track (Session 7): Processors |
Antonio Gonzalez, Universitat Politecnica de Catalunya, Spain; Intel Barcelona Research Center, Spain pp. 225-234
Yoav Etsion, The Hebrew University of Jerusalem, Israel pp. 235-244
 | Software Track (Session 8): Compilers |
Jeremy Lau, University of California, San Diego, USA pp. 259-269
Long Li, Intel China Software Center, China pp. 270-279
 | Hardware Track (Session 9): Modeling & Measurement |
Mateo Valero, Barcelona Supercomputing Center, Spain; Universitat Politecnica de Catalunya, Spain pp. 305-316
John H. Kelm, University of Illinois at Urbana-Champaign, USA
Wen-mei Hwu, University of Illinois at Urbana-Champaign, USA pp. 317-326
 | Software Track (Session 10): Transactional Memory & Locks |
 | Poster Abstracts |
Feihui Li, The Pennsylvania State University, USA pp. 401
Changjun Hu, University of Science and Technology Beijing, China
Jilin Zhang, University of Science and Technology Beijing, China
Jue Wang, University of Science and Technology Beijing, China
Jianjiang Li, University of Science and Technology Beijing, China
Liang Ding, University of Science and Technology Beijing, China pp. 410
Wei Chen, University of California at Berkeley, USA pp. 411
Denis Barthou, University of Versailles-Saint-Quentin-en-Yvelines, France pp. 415
Dana Petcu, Western University of Timisoara, Romania pp. 417
Alex Ramirez, Universitat Politecnica de Catalunya, Spain; Barcelona Supercomputing Center, Spain
Mateo Valero, Universitat Politecnica de Catalunya, Spain; Barcelona Supercomputing Center, Spain pp. 418
D. Soudris, Democritus University of Thrace, Greece
N. Voros, Intracom Telecom Solutions, Greece pp. 421
Feng Mao, The College of William and Mary, USA pp. 426
R. Ubal, Universidad Politecnica de Valencia, Spain
S. Petit, Universidad Politecnica de Valencia, Spain
P. Lopez, Universidad Politecnica de Valencia, Spain
J. Duato, Universidad Politecnica de Valencia, Spain pp. 429
Jing Yu, University of Illinois at Urbana-Champaign, USA pp. 433
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