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13th International Conference on Parallel Architecture and Compilation Techniques (PACT'04)
Antibes Juan-les-Pins, France
September 29-October 03
ISBN: 0-7695-2229-7
Table of Contents
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Reviewers (PDF)
pp. xii-xiii
Keynote Address
Wen-Mei Hwu, University of Illinois at Champaign-Urbana, USA
pp. 3-3
Session 1: Code Generation
C?dric Bastoul, Universit? de Versailles Saint Quentin, France
pp. 7-16
Jin Lin, University of Minnesota
Wei-Chung Hsu, University of Minnesota
Pen-Chung Yew, University of Minnesota
Roy Dz-Ching Ju, Intel Corporation, Santa Clara, CA
Tin-Fook Ngai, Intel Corporation, Santa Clara, CA
pp. 17-28
Yuri Dotsenko, Rice University, Houston, TX
Cristian Coarfa, Rice University, Houston, TX
John Mellor-Crummey, Rice University, Houston, TX
pp. 29-40
Session 2: Architecture
Marc Epalza, Signal Processing Institute
Paolo Ienne, Processor Architecture Lab
Daniel Mlynek, Signal Processing Institute
pp. 53-62
Alex Settle, University of Colorado at Boulder
Joshua Kihm, University of Colorado at Boulder
Andrew Janiszewski, University of Colorado at Boulder
Dan Connors, University of Colorado at Boulder
pp. 63-73
Ramadass Nagarajan, The University of Texas at Austin
Sundeep K. Kushwaha, The University of Texas at Austin
Doug Burger, The University of Texas at Austin
Kathryn S. McKinley, The University of Texas at Austin
Calvin Lin, The University of Texas at Austin
Stephen W. Keckler, The University of Texas at Austin
pp. 74-84
Leonardo Bachega, IBM T. J. Watson Research Center, Yorktown Heights, NY
Siddhartha Chatterjee, IBM T. J. Watson Research Center, Yorktown Heights, NY
Kenneth A. Dockser, IBM Corporation, Research Triangle Park, NC
John A. Gunnels, IBM T. J. Watson Research Center, Yorktown Heights, NY
Manish Gupta, IBM T. J. Watson Research Center, Yorktown Heights, NY
Fred G. Gustavson, IBM T. J. Watson Research Center, Yorktown Heights, NY
Christopher A. Lapkowski, IBM Corporation, Markham, ON, Canada
Gary K. Liu, IBM Corporation, Markham, ON, Canada
Mark P. Mendell, IBM Corporation, Markham, ON, Canada
Charles D. Wait, IBM Corporation, Rochester, MN
T. J. Chris Ward, IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 85-96
Session 3: Memory Hierarchy
Tulika Mitra, National University of Singapore
Abhik Roychoudhury, National University of Singapore
Qinghua Shen, National University of Singapore
pp. 99-110
Seongbeom Kim, North Carolina State University
Dhruba Chandra, North Carolina State University
Yan Solihin, North Carolina State University
pp. 111-122
Weidong Shi, Georgia Institute of Technology, Atlanta, GA
Hsien-Hsin S. Lee, Georgia Institute of Technology, Atlanta, GA
Mrinmoy Ghosh, Georgia Institute of Technology, Atlanta, GA
Chenghuai Lu, Georgia Institute of Technology, Atlanta, GA
pp. 123-134
Kyle J. Nesbit, University of Wisconsin - Madison
Ashutosh S. Dhodapkar, University of Wisconsin - Madison
James E. Smith, University of Wisconsin - Madison
pp. 135-145
Session 4: Compiler Optimizations
YongKang Zhu, University of Rochester, New York
Grigorios Magklis, Intel Barcelona Research Center, Barcelona, Spain
Michael L. Scott, University of Rochester, New York
Chen Ding, University of Rochester, New York
David H. Albonesi, University of Rochester, New York
pp. 153-164
Dhruva R. Chakrabarti, Hewlett-Packard Company, Cupertino, CA
Luis A. Lozano, Hewlett-Packard Company, Cupertino, CA
Xinliang D. Li, Hewlett-Packard Company, Cupertino, CA
Robert Hundt, Hewlett-Packard Company, Cupertino, CA
Shin-Ming Liu, Hewlett-Packard Company, Cupertino, CA
pp. 165-176
Ram Rangan, Princeton University
Neil Vachharajani, Princeton University
Manish Vachharajani, Princeton University
David I. August, Princeton University
pp. 177-188
Wen Xu, Princeton University
Sanjeev Kumar, Intel Corporation
Kai Li, Princeton University
pp. 189-200
Session 5: Parallel Systems
Jialin Dou, University of Edinburgh, UK
Marcelo Cintra, University of Edinburgh, UK
pp. 203-214
Gladys Utrera, Universitat Polit?cnica de Catalunya (UPC)
Julita Corbal?, Universitat Polit?cnica de Catalunya (UPC)
Jes? Labarta, Universitat Polit?cnica de Catalunya (UPC)
pp. 215-224
Michael Ball, Sun Microsystems, Menlo Park, CA
Cristina Cifuentes, Sun Microsystems Labs, Mountain View, CA
Deepankar Bairagi, Sun Microsystems, Menlo Park, CA
pp. 225-236
Session 6: Memory Parallelism
Silvius Rus, Texas A&M University
Dongmin Zhang, Texas A&M University
Lawrence Rauchwerger, Texas A&M University
pp. 243-254
Takeshi Ogasawara, Tokyo Research Laboratory, IBM Japan
Hideaki Komatsu, Tokyo Research Laboratory, IBM Japan
Toshio Nakatani, Tokyo Research Laboratory, IBM Japan
pp. 255-266
Francois Labonte, Stanford University
Peter Mattson, Reservoir Labs
Ian Buck, Stanford University
Christos Kozyrakis, Stanford University
Mark Horowitz, Stanford University
pp. 267-277
Hao Yu, IBM T. J. Watson Research Ctr, Yorktown Heights, NY
Dongmin Zhang, Texas A&M University
Lawrence Rauchwerger, Texas A&M University
pp. 278-289
Author Index (PDF)
pp. 291-291
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