loading...
  • P
  • PACT
  • 2003
  • 12th International Conference on Parallel Architectures and Compilation Techniques (PACT'03)
Advanced Search 
12th International Conference on Parallel Architectures and Compilation Techniques (PACT'03)
New Orleans, Louisiana
September 27-October 01
ISBN: 0-7695-2021-9
Table of Contents
Introduction
Keynote 1
Session 1: Multithreading
Harold W. Cain, University of Wisconsin-Madison
Mikko H. Lipasti, University of Wisconsin-Madison
Ravi Nair, IBM T.J. Watson Research Center
pp. 4
Session 2: Instruction-Level Parallelism
Dong-Yuan Chen, Intel Corporation
Lixia Liu, Intel Corporation
Chen Fu, Chinese Academy of Sciences
Shuxin Yang, Chinese Academy of Sciences
Chengyong Wu, Chinese Academy of Sciences
Roy Ju, Intel Corporation
pp. 36
Nicholas Wang, University of Illinois at Urbana-Champaign
Michael Fertig, University of Illinois at Urbana-Champaign
Sanjay Patel, University of Illinois at Urbana-Champaign
pp. 56
Session 3: Cache Optimizations
Xavier Vera, Mälardalens Högskola
Jaume Abella, Universitat Politècnica de Catalunya-Barcelona
Antonio González, Universitat Politècnica de Catalunya-Barcelona
Josep Llosa, Universitat Politècnica de Catalunya-Barcelona
pp. 68
Yutao Zhong, University of Rochester
Steven G. Dropsho, University of Rochester
Chen Ding, University of Rochester
pp. 79
Hassan Al-Sukhni, University of Colorado at Boulder
Ian Bratt, University of Colorado at Boulder
Daniel A. Connors, University of Colorado at Boulder
pp. 91
Keynote 2
Session 4: Compiler Techniques and Domain-Specific Optimizations
John Ng, Intel Compiler Laboratory
Dattatraya Kulkarni, Intel Compiler Laboratory
Wei Li, Intel Compiler Laboratory
Robert Cox, Intel Compiler Laboratory
Scott Bobholz, Intel Compiler Laboratory
pp. 114
Akira Koseki, IBM Tokyo Research Laboratory
Hideaki Komatsu, IBM Tokyo Research Laboratory
Toshio Nakatani, IBM Tokyo Research Laboratory
pp. 125
Session 5: Logging, Tracing, Profiling
Toshiaki Yasue, IBM Tokyo Research Laboratory
Toshio Suganuma, IBM Tokyo Research Laboratory
Hideaki Komatsu, IBM Tokyo Research Laboratory
Toshio Nakatani, IBM Tokyo Research Laboratory
pp. 148
María Jesús Garzarán, University of Illinois at Urbana-Champaign
Milos Prvulovic, University of Illinois at Urbana-Champaign
Víctor Viñals, Universidad de Zaragoza
José María Llabería, Universitat Politècnica de Catalunya
Lawrence Rauchwerger, Texas A&M University
Josep Torrellas, University of Illinois at Urbana-Champaign
pp. 170
Session 6: Multiprocessors
Phuong Hoai Ha, Chalmers University of Technology
Philippas Tsigas, Chalmers University of Technology
pp. 184
Jean-Loup Baer, University of Washington
Douglas Low, University of Washington
Patrick Crowley, University of Washington
Neal Sidhwaney, University of Washington
pp. 206
Keynote 3
Session 7: Application Characterization
Kevin M. Lepak, University of Wisconsin-Madison
Harold W. Cain, University of Wisconsin-Madison
Mikko H. Lipasti, University of Wisconsin-Madison
pp. 232
Erez Perelman, University of California at San Diego
Greg Hamerly, University of California at San Diego
Brad Calder, University of California at San Diego
pp. 244
Session 8: Register Design Issues
Dmitry Ponomarev, State University of New York at Binghamton
Gurhan Kucuk, State University of New York at Binghamton
Oguz Ergin, State University of New York at Binghamton
Kanad Ghose, State University of New York at Binghamton
pp. 258
Author Index
Usage of this product signifies your acceptance of the Terms of Use.