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  • Sixth International Conference on Parallel Architectures and Compilation Techniques (PACT'97)
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Sixth International Conference on Parallel Architectures and Compilation Techniques (PACT'97)
San Francisco, CA
November 11-November 15
ISBN: 0-8186-8090-3
Table of Contents
SESSION I. ANALYSIS AND CODE OPTIMIZATIONS: CHAIR: K. Pingali
Xinan Tang, Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
R. Ghiya, Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
L.J. Hendren, Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
G.R. Gao, Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
pp. 14
J. Knoop, Fakultat fur Math. und Inf., Passau Univ., Germany
E. Mehofer, Fakultat fur Math. und Inf., Passau Univ., Germany
pp. 26
SESSION II. NETWORKS/COMMUNICATION OPTIMIZATION: CHAIR: S. Evripidou
Fabrizio Petrini, International Computer Science Institute, (ICSI)
Marco Vanneschi, Dipartimento di Informatica
pp. 52
D.R. Miller, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
W.A. Najjar, Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
pp. 64
SESSION III. ILP OPTIMIZATION/CODE SCHEDULING: CHAIR: M. Valero
SESSION IV. SHORT PAPERS PRESENTATIONS: CHAIR: G. Egan
Carrie J. Brownhill, University of California, Irvine
Alexandru Nicolau, University of California, Irvine
Steve Novack, University of Illinois at Urbana-Champaign
Constantine D. Polychronopoulos, University of Illinois at Urbana-Champaign
pp. 116
Yuetsu Kodama, Electrotechnical Laboratory
Hirofumi Sakane, Electrotechnical Laboratory
Koike Hanpei, Electrotechnical Laboratory
Mitsuhisa Sato, Electrotechnical Laboratory
Shuichi Sakai, Electrotechnical Laboratory
Yoshinori Yamaguchi, Electrotechnical Laboratory
pp. 136
SESSION V. PROFILING AND PREDICTION BASED OPTIMIZATIONS: CHAIR: W. Najjar
K.N. Menezes, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
S.W. Sathaye, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
T.M. Coate, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 178
J.K. Hollingsworth, Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
O. Niam, Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
B.P. Miller, Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
Zhichen Xu, Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
M.J.R. Goncalves, Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
Ling Zheng, Dept. of Comput. Sci., Maryland Univ., College Park, MD, USA
pp. 201
SESSION VI. COMPILATION ISSUES FOR MULTIPROCESSORS: CHAIR: B. Shirazi
M. Kandemir, Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., NY, USA
J. Ramanujam, Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., NY, USA
A. Choudhary, Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., NY, USA
pp. 236
SESSION VII. COMPILER/ARCHITECTURE INTERACTION IN PARALLELISM EXPLOITATION: CHAIR: D. Albonesi
Luis Villa, Insatituto Politecnico Nacional de Mexico D.F.
Roger Espasa, Universitat Politecnica de Catalunya--Barcelona
Mateo Valero, Universitat Politecnica de Catalunya--Barcelona
pp. 250
F. Jesus Sanchez, Universitat Politecnica de Catalunya
Antonio Gonzalez, Universitat Politecnica de Catalunya
Mateo Valero, Universitat Politecnica de Catalunya
pp. 261
SESSION VIII. HIGH-LEVEL PARALLELIZATION: CHAIR: A. Sohn
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