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  • Fifth International Conference on Parallel Architectures and Compilation Techniques (PACT'96)
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Fifth International Conference on Parallel Architectures and Compilation Techniques (PACT'96)
Boston, MA
October 20-October 23
ISBN: 0-8186-7632-9
Table of Contents
Session I. Multithreaded Architectures and Compilation
L.J. Hendren, Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
Xinan Tang, Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
Yingchun Zhu, Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
G.R. Gao, Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
Xun Xue, Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
Haiying Cai, Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
P. Ouellet, Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
pp. 0012
Session II. Forecasting Branches and Memory Access
Stephan Jourdan, Universite Paul Sabatier
Tse-Hao Hsing, The University of Michigan
Jared Stark, The University of Michigan
Yale N. Patt, The University of Michigan
pp. 0058
Session III. New Techniques in Instruction-Level Parallelism
P. Tinumalai, Sun Microsystems Inc., Mountain View, CA, USA
B. Beylin, Sun Microsystems Inc., Mountain View, CA, USA
K. Subramanian, Sun Microsystems Inc., Mountain View, CA, USA
pp. 0097
Session IV. Short Papers and Posters
K. Okamato, RWC Tsukuba Res. Center, Ibaraki, Japan
S. Sakai, RWC Tsukuba Res. Center, Ibaraki, Japan
H. Matsuoka, RWC Tsukuba Res. Center, Ibaraki, Japan
T. Yokota, RWC Tsukuba Res. Center, Ibaraki, Japan
H. Hirono, RWC Tsukuba Res. Center, Ibaraki, Japan
pp. 0116
A. Sohn, New Jersey Institute of Technology
J. Ku, New Jersey Institute of Technology
Y. Kodama, Electrotechnical Laboratory
M. Sato, Electrotechnical Laboratory
H. Sakane, Electrotechnical Laboratory
H. Yamana, Electrotechnical Laboratory
S. Sakai, Electrotechnical Laboratory
Y. Yamaguchi, Electrotechnical Laboratory
pp. 0133
A. Goikhman, Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
J. Katzenelson, Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
pp. 0144
Dmitry Arapov, Russian Academy of Sciences
Alexey Kalinov, Russian Academy of Sciences
Alexey Lastovetsky, Russian Academy of Sciences
pp. 0150
Mat Loikkanen, University of California, Irvine
Nader Bagherzadeh, University of California, Irvine
pp. 0163
M. Al-Mouhamed, Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
L. Bic, Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
H. Abu-Haimed, Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
pp. 0174
Session V. Applications and Tools
Andrew Shaw, Massachusetts Institute of Technology
R. Arvind, Massachusetts Institute of Technology
Paul Johnson, Massachusetts Institute of Technology
pp. 0198
D. Abramson, Sch. of Comput. & Inf. Technol., Griffith Univ., Brisbane, Qld., Australia
R. Sosic, Sch. of Comput. & Inf. Technol., Griffith Univ., Brisbane, Qld., Australia
C. Watson, Sch. of Comput. & Inf. Technol., Griffith Univ., Brisbane, Qld., Australia
pp. 0218
Session VI. Compiler Techniques and Memory Hierarchies
Shin-Ming Liu, Silicon Graphics Computer Systems
Raymond Lo, Silicon Graphics Computer Systems
Fred Chow, Silicon Graphics Computer Systems
pp. 0228
Session VIII. Automatic Parallelization and Applications
A. Darte, Lab. LIP, Ecole Normale Superieure de Lyon, France
F. Vivien, Lab. LIP, Ecole Normale Superieure de Lyon, France
pp. 0281
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