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2009 Pacific-Asia Conference on Circuits, Communications and Systems
A Framework for Software Performance Simulation Using Binary to C Translation
Chengdu, China
May 16-May 17
ISBN: 978-0-7695-3614-9
| ASCII Text | x | ||
| Binjie Xiao, Ke Wang, Weiqun Shu, "A Framework for Software Performance Simulation Using Binary to C Translation," Circuits, Communications and Systems, Pacific-Asia Conference on, pp. 602-605, 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/PACCS.2009.57, author = {Binjie Xiao and Ke Wang and Weiqun Shu}, title = {A Framework for Software Performance Simulation Using Binary to C Translation}, journal ={Circuits, Communications and Systems, Pacific-Asia Conference on}, volume = {0}, year = {2009}, isbn = {978-0-7695-3614-9}, pages = {602-605}, doi = {http://doi.ieeecomputersociety.org/10.1109/PACCS.2009.57}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Circuits, Communications and Systems, Pacific-Asia Conference on TI - A Framework for Software Performance Simulation Using Binary to C Translation SN - 978-0-7695-3614-9 SP602 EP605 A1 - Binjie Xiao, A1 - Ke Wang, A1 - Weiqun Shu, PY - 2009 KW - compiled simulator KW - binary to C translation KW - MPSoC VL - 0 JA - Circuits, Communications and Systems, Pacific-Asia Conference on ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PACCS.2009.57
This Paper presents the realization of a simple but efficient technique to increase the performance of the processor simulator, which can be used both for software performance evaluation or hardware performance evaluation, such as MPSoC. Due to the fast increasing of the software complexity, it brings forward more requirements on the speed of the processor simulation, which simulates a certain target processor (such as PowerPC, ARM etc.) on certain host platform (usually PC ). The performance improvement of a processor simulator can enlarge the exploration space and shorten the time-to-market. The existing approaches use either interpretive simulator or complied simulator or a binary translator. This paper performs binary to C translation to generate the processor simulator.
Index Terms:
compiled simulator, binary to C translation, MPSoC
Citation:
Binjie Xiao, Ke Wang, Weiqun Shu, "A Framework for Software Performance Simulation Using Binary to C Translation," paccs, pp.602-605, 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009
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