|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
2009 Pacific-Asia Conference on Circuits, Communications and Systems
Low-power Capacitor Arrays for Charge Redistribution SAR A-D Converter in 65nm CMOS
Chengdu, China
May 16-May 17
ISBN: 978-0-7695-3614-9
| ASCII Text | x | ||
| Xingyuan Tong, Zhangming Zhu, Yintang Yang, "Low-power Capacitor Arrays for Charge Redistribution SAR A-D Converter in 65nm CMOS," Circuits, Communications and Systems, Pacific-Asia Conference on, pp. 293-296, 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/PACCS.2009.105, author = {Xingyuan Tong and Zhangming Zhu and Yintang Yang}, title = {Low-power Capacitor Arrays for Charge Redistribution SAR A-D Converter in 65nm CMOS}, journal ={Circuits, Communications and Systems, Pacific-Asia Conference on}, volume = {0}, year = {2009}, isbn = {978-0-7695-3614-9}, pages = {293-296}, doi = {http://doi.ieeecomputersociety.org/10.1109/PACCS.2009.105}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Circuits, Communications and Systems, Pacific-Asia Conference on TI - Low-power Capacitor Arrays for Charge Redistribution SAR A-D Converter in 65nm CMOS SN - 978-0-7695-3614-9 SP293 EP296 A1 - Xingyuan Tong, A1 - Zhangming Zhu, A1 - Yintang Yang, PY - 2009 KW - SAR A/D converter KW - charge sharing architecture KW - capacitor splitting architecture KW - two-step architecture KW - low power VL - 0 JA - Circuits, Communications and Systems, Pacific-Asia Conference on ER - | |||
Through the research on charge redistribution SAR A/D converter, three energy-efficient capacitor arrays are discussed in this paper. The switching energy of the traditional architecture, charge sharing architecture, capacitor splitting architecture and two-step architecture capacitor arrays is derived and analyzed. Based on SMIC 65nm CMOS process, 10-bit SAR A/D converters of all these architectures are designed to validate these concepts. The energy dissipation from Hspice simulation is discussed. At the smallest output code, charge sharing architecture and capacitor splitting architecture consume respectively 65.5% and 44.8% of the energy conventional architecture dissipates. At the smallest and largest output codes, two-step architecture just consumes respectively 10.4% and 23.1% of the traditional architecture’s dissipation.
Index Terms:
SAR A/D converter, charge sharing architecture, capacitor splitting architecture, two-step architecture, low power
Citation:
Xingyuan Tong, Zhangming Zhu, Yintang Yang, "Low-power Capacitor Arrays for Charge Redistribution SAR A-D Converter in 65nm CMOS," paccs, pp.293-296, 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009
Usage of this product signifies your acceptance of the Terms of Use.