3&lt;sup&gt;rd&lt;/sup&gt; ACM/IEEE international symposium on networks-on-chip

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Adaptive stochastic routing in fault-tolerant on-chip networks (Abstract)

Wei Song, School of Computer Science, University of Manchester, M13 9PL UK

Doug Edwards, School of Computer Science, University of Manchester, M13 9PL UK

Jose Luis Nunez-Yanez, Department of Electrical and Electronic Engineering, Bristol University, BS8 1UB UK

Sohini Dasgupta, School of Computer Science, University of Manchester, M13 9PL UK

pp. 32-37

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Static virtual channel allocation in oblivious routing (Abstract)

Keun Sup Shim, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA

Myong Hyon Cho, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA

Michel Kinsy, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA

Tina Wen, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA

Mieszko Lis, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA

G. Edward Suh, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA

Srinivas Devadas, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA

pp. 38-43

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Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip (Abstract)

Yue Qian, School of Computer Science, National University of Defense Technology, China

Zhonghai Lu, Dept. of Electronic, Computer and Software Systems, Royal Institute of Technology (KTH), Sweden

Wenhua Dou, School of Computer Science, National University of Defense Technology, China

pp. 44-53

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Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links (Abstract)

Bo Fu, Dept. of Electrical and Computer Engineering, University of Rochester, NY 14627, USA

David Wolpert, Dept. of Electrical and Computer Engineering, University of Rochester, NY 14627, USA

Paul Ampadu, Dept. of Electrical and Computer Engineering, University of Rochester, NY 14627, USA

pp. 54-63

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Recursive partitioning multicast: A bandwidth-efficient routing for Networks-on-Chip (Abstract)

Lei Wang, Department of Computer Science and Engineering, Texas A&M University, College Station, 77843 USA

Yuho Jin, Department of Computer Science and Engineering, Texas A&M University, College Station, 77843 USA

Hyungjun Kim, Department of Computer Science and Engineering, Texas A&M University, College Station, 77843 USA

Eun Jung Kim, Department of Computer Science and Engineering, Texas A&M University, College Station, 77843 USA

pp. 64-73

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Energy efficient application mapping to NoC processing elements operating at multiple voltage levels (Abstract)

Pavel Ghosh, Department of Computer Science and Engineering, Arizona State University, Tempe, USA

Arunabha Sen, Department of Computer Science and Engineering, Arizona State University, Tempe, USA

Alexander Hall, Department of EECS, UC Berkeley, CA, USA

pp. 80-85

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The design of a latency constrained, power optimized NoC for a 4G SoC (Abstract)

Rudy Beraha, Qualcomm Corp. Research and Development, San Diego, California 92121, USA

Isask'har Walter, Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa 32000, Israel

Israel Cidon, Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa 32000, Israel

Avinoam Kolodny, Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa 32000, Israel

pp. 86

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Performance Evaluation of NoC Architectures for Parallel Workloads (Abstract)

Henrique C. Freitas

Marco A. Z. Alves, Informatics Institute, Universidade Federal do Rio Grande do Sul, RS, Brazil

Lucas M. Schnorr, Informatics Institute, Universidade Federal do Rio Grande do Sul, RS, Brazil

Philippe O. A. Navaux, Informatics Institute, Universidade Federal do Rio Grande do Sul, RS, Brazil

pp. 87

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Packet-level static timing analysis for NoCs (Abstract)

Evgeni Krimer, Department of Electrical and Computer Engineering, University of Texas at Austin, USA

Mattan Erez, Department of Electrical and Computer Engineering, University of Texas at Austin, USA

Isaac Keslassy, Department of Electrical Engineering, Technion-Israel Institute of Technology, Israel

Avinoam Kolodny, Department of Electrical Engineering, Technion-Israel Institute of Technology, Israel

Isask'har Walter, Department of Electrical Engineering, Technion-Israel Institute of Technology, Israel

pp. 88

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Increasing NoC power estimation accuracy through a rate-based model (Abstract)

Guilherme Guindani, PUCRS, Av. Ipiranga 6681, P. 32, Porto Alegre, Brazil

Cezar Reinbrecht, PUCRS, Av. Ipiranga 6681, P. 32, Porto Alegre, Brazil

Thiago R. da Rosa, PUCRS, Av. Ipiranga 6681, P. 32, Porto Alegre, Brazil

Fernando Moraes, PUCRS, Av. Ipiranga 6681, P. 32, Porto Alegre, Brazil

pp. 89

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On-Chip photonic interconnects for scalable multi-core architectures (Abstract)

Avinash Karanth Kodi, School of Electrical Engineering and Computer Science, Ohio University, Athens, 45701, USA

Randy Morris, School of Electrical Engineering and Computer Science, Ohio University, Athens, 45701, USA

Ahmed Louri, Electrical and Computer Engineering, University of Arizona, Tucson, 85721, USA

Xiang Zhang, Electrical and Computer Engineering, University of Arizona, Tucson, 85721, USA

pp. 90

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A Modeling and exploration framework for interconnect network design in the nanometer era (Abstract)

Ajay Joshi, Department of EECS, Massachusetts Institute of Technology, Cambridge, USA

Fred Chen, Department of EECS, Massachusetts Institute of Technology, Cambridge, USA

Vladimir Stojanovic, Department of EECS, Massachusetts Institute of Technology, Cambridge, USA

pp. 91

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Analysis of photonic networks for a chip multiprocessor using scientific applications (Abstract)

Gilbert Hendry, Lightwave Research Laboratory, Columbia University, New York, 10027, USA

Shoaib Kamil, Computer Science Department, University of California, Berkeley, 94720, USA

Aleksandr Biberman, Lightwave Research Laboratory, Columbia University, New York, 10027, USA

Johnnie Chan, Lightwave Research Laboratory, Columbia University, New York, 10027, USA

Benjamin G. Lee, Lightwave Research Laboratory, Columbia University, New York, 10027, USA

Marghoob Mohiyuddin, Computer Science Department, University of California, Berkeley, 94720, USA

Ankit Jain, Computer Science Department, University of California, Berkeley, 94720, USA

Keren Bergman, Lightwave Research Laboratory, Columbia University, New York, 10027, USA

Luca P. Carloni, Computer Science Department, Columbia University, New York, 10027, USA

John Kubiatowicz, Computer Science Department, University of California, Berkeley, 94720, USA

Leonid Oliker, CRD/NERSC, Lawrence Berkeley National Laboratory, Berkeley, CA 94720, USA

John Shalf, CRD/NERSC, Lawrence Berkeley National Laboratory, Berkeley, CA 94720, USA

pp. 104-113

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Scalability of network-on-chip communication architecture for 3-D meshes (Abstract)

Awet Yemane Weldezion, School of Information and Communication Technologies, Department of Electronics, Computer, and Software Systems, KTH Royal Institute of Technology, Electrum 229, Kista SE 16440, Sw

Matt Grange, Centre for Microsystems Engineering, Department of Engineering, Lancaster University, LA1 4YW, UK

Dinesh Pamunuwa, Centre for Microsystems Engineering, Department of Engineering, Lancaster University, LA1 4YW, UK

Zhonghai Lu, School of Information and Communication Technologies, Department of Electronics, Computer, and Software Systems, KTH Royal Institute of Technology, Electrum 229, Kista SE 16440, Sw

Axel Jantsch, School of Information and Communication Technologies, Department of Electronics, Computer, and Software Systems, KTH Royal Institute of Technology, Electrum 229, Kista SE 16440, Sw

Roshan Weerasekera, Centre for Microsystems Engineering, Department of Engineering, Lancaster University, LA1 4YW, UK

Hannu Tenhunen, Centre for Microsystems Engineering, Department of Engineering, Lancaster University, LA1 4YW, UK

pp. 114-123

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Silicon-photonic clos networks for global on-chip communication (Abstract)

Ajay Joshi, Department of EECS, Massachusetts Institute of Technology, Cambridge, USA

Christopher Batten, Department of EECS, Massachusetts Institute of Technology, Cambridge, USA

Yong-Jin Kwon, Department of EECS, University of California, Berkeley, USA

Scott Beamer, Department of EECS, University of California, Berkeley, USA

Imran Shamim, Department of EECS, Massachusetts Institute of Technology, Cambridge, USA

Krste Asanovic, Department of EECS, University of California, Berkeley, USA

Vladimir Stojanovic, Department of EECS, Massachusetts Institute of Technology, Cambridge, USA

pp. 124-133

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A Communication and configuration controller for NoC based reconfigurable data flow architecture (Abstract)

Fabien Clermidy, CEA, LETI, MINATEC, F38054 GRENOBLE Cedex 9, FRANCE

Romain Lemaire, CEA, LETI, MINATEC, F38054 GRENOBLE Cedex 9, FRANCE

Yvain Thonnart, CEA, LETI, MINATEC, F38054 GRENOBLE Cedex 9, FRANCE

Pascal Vivet, CEA, LETI, MINATEC, F38054 GRENOBLE Cedex 9, FRANCE

pp. 153-162

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Best of both worlds: A bus enhanced NoC (BENoC) (Abstract)

Ran Manevich, Electrical Engineering Department, Technion - Israel Institute of Technology, Israel

Isask'har Walter, Electrical Engineering Department, Technion - Israel Institute of Technology, Israel

Israel Cidon, Electrical Engineering Department, Technion - Israel Institute of Technology, Israel

Avinoam Kolodny, Electrical Engineering Department, Technion - Israel Institute of Technology, Israel

pp. 173-182

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CTC: An end-to-end flow control protocol for multi-core systems-on-chip (Abstract)

Nicola Concer, Dipartimento di Scienze dell'Informazione, Università di Bologna, Italy

Luciano Bononi, Dipartimento di Scienze dell'Informazione, Università di Bologna, Italy

Michael Soulie, ST Microelectronics, Grenoble, France

Riccardo Locatelli, ST Microelectronics, Grenoble, France

Luca P. Carloni, Computer Science Department, Columbia University in the City of New York, USA

pp. 193-202

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Performance and power efficient on-chip communication using adaptive virtual point-to-point connections (Abstract)

Mehdi Modarressi, Sharif University of Technology, Tehran, Iran

Hamid Sarbazi-Azad, Sharif University of Technology, Tehran, Iran

Arash Tavakkol, Sharif University of Technology, Tehran, Iran

pp. 203-212

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A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network (Abstract)

Anh T. Tran, Department of Electrical and Computer Engineering, University of California - Davis, USA

Dean N. Truong, Department of Electrical and Computer Engineering, University of California - Davis, USA

Bevan M. Baas, Department of Electrical and Computer Engineering, University of California - Davis, USA

pp. 214-223

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Estimating reliability and throughput of source-synchronous wave-pipelined interconnect (Abstract)

Paul Teehan, University of British Columbia, Vancouver, Canada

Guy G.F. Lemieux, University of British Columbia, Vancouver, Canada

Mark R. Greenstreet, University of British Columbia, Vancouver, Canada

pp. 234-243

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Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture (Abstract)

Daniele Ludovici, Computer Engineering Lab., Delft University of Technology, The Netherlands

Alessandro Strano, ENDIF, University of Ferrara, 44100, Italy

Davide Bertozzi, DEIS, University of Bologna, 40136, Italy

Luca Benini, Computer Engineering Lab., Delft University of Technology, The Netherlands

Georgi N. Gaydadjiev, Computer Engineering Lab., Delft University of Technology, The Netherlands

pp. 244-249

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Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers (Abstract)

Young Hoon Kang, University of Southern California / Information Sciences Institute, USA

Taek-Jun Kwon, University of Southern California / Information Sciences Institute, USA

Jeff Draper, University of Southern California / Information Sciences Institute, USA

pp. 250-255

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Diagnosis of interconnect shorts in mesh NoCs (Abstract)

Marcos Herve, Universidade Federal do Rio Grande do Sul, PPGC - PGMICRO - Instituto de Informática / Escola de Engenharia, P.O. Box 15064, ZIP 91501-970, Porto Alegre, Brazil

Erika Cota, Universidade Federal do Rio Grande do Sul, PPGC - PGMICRO - Instituto de Informática / Escola de Engenharia, P.O. Box 15064, ZIP 91501-970, Porto Alegre, Brazil

Fernanda Lima Kastensmidt, Universidade Federal do Rio Grande do Sul, PPGC - PGMICRO - Instituto de Informática / Escola de Engenharia, P.O. Box 15064, ZIP 91501-970, Porto Alegre, Brazil

Marcelo Lubaszewski, Universidade Federal do Rio Grande do Sul, PPGC - PGMICRO - Instituto de Informática / Escola de Engenharia, P.O. Box 15064, ZIP 91501-970, Porto Alegre, Brazil

pp. 256-265

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