Systems-on-chip designs often use functional blocks operating at different clock frequencies. This motivates the use of an asynchronous network-on-chip (NoC) with synchronizing FIFOs interfacing between the NoC and the functional blocks. To minimize design time, these FIFOs should be constructed from cells available in a standard cell library and configurable to work in a wide range of applications. We present a modular synchronizing FIFO design that can be implemented using logic gates from a typical standard-cell library. The FIFO has interchangeable input and output interfaces for edge-triggered synchronous communication and for two asynchronous handshake protocols: asP* and LEDR. The FIFO capacity, synchronizer latency and interface protocols are independent parameters, allowing the FIFO to be easily configured for different NoC requirements. We evaluate performance using post-layout simulation results and analyze the metastability induced failure rate for synchronization latencies from half a clock cycle up to three clock cycles.